 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Features * Incorporates the ARM926EJ-STM ARM(R) Thumb(R) Processor - DSP Instruction Extensions, ARM Jazelle(R) Technology for Java(R) Acceleration - 32-KByte Data Cache, 32-KByte Instruction Cache, Write Buffer - CPU Frequency 400 MHz - Memory Management Unit - EmbeddedICETM, Debug Communication Channel Support Additional Embedded Memories - One 64-KByte Internal ROM, Single-cycle Access at Maximum Matrix Speed - Two 16-KByte Internal SRAM, Single-cycle Access at Maximum Matrix Speed External Bus Interface (EBI) - Supports SDRAM, Static Memory, ECC-enabled SLC NAND Flash and CompactFlash(R) USB 2.0 Full Speed (12 Mbits per second) Device Port - On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM USB 2.0 Full Speed (12 Mbits per second) Host and Dual Port - Single or Dual On-chip Transceivers - Integrated FIFOs and Dedicated DMA Channels Ethernet MAC 10/100 Base T - Media Independent Interface or Reduced Media Independent Interface - 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit Image Sensor Interface - ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate - 12-bit Data Interface for Support of High Sensibility Sensors - SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format Bus Matrix - Six 32-bit-layer Matrix - Boot Mode Select Option, Remap Command Fully-featured System Controller, including - Reset Controller, Shutdown Controller - Four 32-bit Battery Backup Registers for a Total of 16 Bytes - Clock Generator and Power Management Controller - Advanced Interrupt Controller and Debug Unit - Periodic Interval Timer, Watchdog Timer and Real-time Timer Reset Controller (RSTC) - Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control Clock Generator (CKGR) - Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock - 3 to 20 MHz On-chip Oscillator, One up to 800 MHz PLL and One up to 100 MHz PLL Power Management Controller (PMC) - Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities - Two Programmable External Clock Signals Advanced Interrupt Controller (AIC) - Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) - 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention * * * * AT91 ARM Thumb Microcontrollers AT91SAM9G20 Preliminary * * * * * * * * * 6384D-ATARM-04-May-09 - Mode for General Purpose 2-wire UART Serial Communication * Periodic Interval Timer (PIT) - 20-bit Interval Timer plus 12-bit Interval Counter * Watchdog Timer (WDT) - Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock * Real-time Timer (RTT) - 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler * One 4-channel 10-bit Analog-to-Digital Converter * Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC) - 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output - All I/O Lines are Schmitt Trigger Inputs Peripheral DMA Controller Channels (PDC) One Two-slot MultiMedia Card Interface (MCI) - SDCard/SDIO and MultiMediaCardTM Compliant - Automatic Protocol Control and Fast Automatic Data Transfers with PDC One Synchronous Serial Controller (SSC) - Independent Clock and Frame Sync Signals for Each Receiver and Transmitter - IS Analog Interface Support, Time Division Multiplex Support - High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Four Universal Synchronous/Asynchronous Receiver Transmitters (USART) - Individual Baud Rate Generator, IrDA(R) Infrared Modulation/Demodulation, Manchester Encoding/Decoding - Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support - Full Modem Signal Control on USART0 Two 2-wire UARTs Two Master/Slave Serial Peripheral Interfaces (SPI) - 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects - Synchronous Communications Two Three-channel 16-bit Timer/Counters (TC) - Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability - High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2 One Two-wire Interface (TWI) - Compatible with Standard Two-wire Serial Memories - One, Two or Three Bytes for Slave Address - Sequential Read/Write Operations - Master, Multi-master and Slave Mode Operation - Bit Rate: Up to 400 Kbits - General Call Supported in Slave Mode - Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode IEEE(R) 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies - 0.9V to 1.1V for VDDBU, VDDCORE, VDDPLL - 1.65 to 3.6V for VDDOSC - 1.65V to 3.6V for VDDIOP (Peripheral I/Os) - 3.0V to 3.6V for VDDUSB - 3.0V to 3.6V VDDANA (Analog-to-digital Converter) - Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os) Available in a 217-ball LFBGA and 247-ball TFBGA RoHS-compliant Package * * * * * * * * * * * 2 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 1. Description The AT91SAM9G20 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The AT91SAM9G20 embeds an Ethernet MAC, one USB Device Port, and a USB Host controller. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface. The AT91SAM9G20 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide range of memory devices. The AT91SAM9G20 is an enhancement of the AT91SAM9260 with the same peripheral features. It is pin-to-pin compatible with the exception of power supply pins. Speed is increased to reach 400 MHz on the ARM core and 133 MHz on the system bus and EBI. 3 6384D-ATARM-04-May-09 Figure 2-1. MASTER L S TD TDI TMO TC S RTK CK JT AG SE ET EX T CK EX C EN ER ERRS -E XC T ERXE -EC XE K ROR EX T 0- -ER L M X0 ER XD D- X M C ETX 3 V D 3 F1 IO 00 TST Transc. Transc. In-Circuit Emulator System Controller JTAG Selection and Boundary Scan FIQ IRQ0-IRQ2 AIC DBGU ICache 32K bytes MMU Bus Interface DCache 32K bytes ARM926EJ-S Processor USB OHCI FIFO DMA DMA DMA D FIFO BM 10/100 Ethernet MAC DRXD DTXD PCK0-PCK1 I PDC PMC PLLA AT91SAM9G20 Block Diagram Filter Filter PLLB 2. AT91SAM9G20 Block Diagram XIN XOUT OSC WDT PIT 6-layer Matrix RC 4GPREG G TW CTD T WC K RS T 0SC S0 CT S RX K0 -RT 3 -S TXD0- SCK3 D0 RX 2 -T D5 X DS D5 DCR0 D0 R DT I0 R0 M CD B0 -M CD M CD MC B3 CD A 0MB C M DA C CD 3 MA CC K NP NC PS NPCS3 NPCS2 C1 SP S0 M CK O T M SI CL IS O TI K0 O -T TI A0- CL O TK TC B0 IO 2 L -T A2 TI K3 IOB OTI A3 TC 2 L O B3-TIOK5 -T A IO 5 B5 TK TF TD RD RF RK AD 0AD AD 3 TR IG AD VR EF V DD AN A ND AN A 6384D-ATARM-04-May-09 SPI0_, SPI1_ DD DDM P AT91SAM9G20 Preliminary PIOA PIOB PIOC Peripheral Bridge 24-channel Peripheral DMA ROM 64 Kbytes Fast SRAM 16 Kbytes Fast SRAM 16 Kbytes APB SDRAM Controller PDC PDC SPI0 SPI1 TC0 TC1 TC2 TC3 TC4 TC5 SSC PDC PDC TWI PDC DPRAM OSCSEL XIN32 XOUT32 OSC RTT SHDN WKUP VDDBU SHDC POR VDDCORE POR RSTC NRST PDC MCI 4-channel 10-bit ADC USART0 USART1 USART2 USART3 USART4 USART5 IS I_ M IS CK I_ IS PC I_ K IS DO I_ -I V IS S SI I_ YN _D7 HS C YN C H D HD PA M A Image Sensor Interface EBI CompactFlash NAND Flash USB Device Static Memory Controller ECC Controller Transceiver HD P HD B M B 4 D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A20 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK, SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE A21/NANDALE, A22/NANDCLE D16-D31 NWAIT A23-A24 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW CFCE1-CFCE2 NCS2, NCS6, NCS7 NCS3/NANDCS SLAVE AT91SAM9G20 Preliminary 3. Signal Description Table 3-1. Signal Name Signal Description List (Continued) Function Power Supplies Type Active Level Comments VDDIOM VDDIOP VDDBU VDDANA VDDPLL VDDOSC VDDCORE VDDUSB GND GNDANA GNDBU GNDUSB GNDPLL EBI I/O Lines Power Supply Peripherals I/O Lines Power Supply Backup I/O Lines Power Supply Analog Power Supply PLL Power Supply Oscillator Power Supply Core Chip Power Supply USB Power Supply Ground Analog Ground Backup Ground USB Ground PLL Ground Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground 1.65V to 1.95V or 3.0V to 3.6V 1.65V to 3.6V 0.9V to 1.1V 3.0V to 3.6V 0.9V to 1.1V 1.65V to 3.6V 0.9V to 1.1V 1.65V to 3.6V Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 OSCSEL PCK0 - PCK1 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Slow Clock Oscillator Selection Programmable Clock Output Input Output Input Output Input Output Accepts between 0V and VDDBU. Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-up Input ICE and JTAG NTRST TCK TDI TDO TMS JTAGSEL RTCK Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Return Test Clock Input Input Input Output Input Input Output No pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU. Low Pull-up resistor No pull-up resistor No pull-up resistor Output Input Accepts between 0V and VDDBU. 5 6384D-ATARM-04-May-09 Table 3-1. Signal Name Signal Description List (Continued) Function Reset/Test Type Active Level Comments NRST TST Microcontroller Reset Test Mode Select I/O Input Low Pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU. No pull-up resistor BMS = 0 when tied to GND. BMS = 1 when tied to VDDIOP. BMS Boot Mode Select Debug Unit - DBGU Input DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Advanced Interrupt Controller - AIC IRQ0 - IRQ2 FIQ External Interrupt Inputs Fast Interrupt Input Input Input PIO Controller - PIOA - PIOB - PIOC PA0 - PA31 PB0 - PB31 PC0 - PC31 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C I/O I/O I/O Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset External Bus Interface - EBI D0 - D31 A0 - A25 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Low Pulled-up input at reset 0 at reset Static Memory Controller - SMC NCS0 - NCS7 NWR0 - NWR3 NRD NWE NBS0 - NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output CompactFlash Support CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 - CFCS1 CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines Output Output Output Output Output Output Output Low Low Low Low Low Low Low Low Low Low Low 6 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 3-1. Signal Name Signal Description List (Continued) Function Type NAND Flash Support Active Level Comments NANDCS NANDOE NANDWE NANDALE NANDCLE NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable NAND Flash Address Latch Enable NAND Flash Command Latch Enable Output Output Output Output Output Low Low Low Low Low SDRAM Controller SDCK SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line Output Output Output Output Output Output Output Low Low High Low Multimedia Card Interface MCI MCCK MCCDA MCDA0 - MCDA3 MCCDB MCDB0 - MCDB3 Multimedia Card Clock Multimedia Card Slot A Command Multimedia Card Slot A Data Multimedia Card Slot B Command Multimedia Card Slot B Data Output I/O I/O I/O I/O Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx TXDx RXDx RTSx CTSx DTR0 DSR0 DCD0 RI0 USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send USART0 Data Terminal Ready USART0 Data Set Ready USART0 Data Carrier Detect USART0 Ring Indicator I/O I/O Input Output Input Output Input Input Input Synchronous Serial Controller - SSC TD RD TK RK TF RF SSC Transmit Data SSC Receive Data SSC Transmit Clock SSC Receive Clock SSC Transmit Frame Sync SSC Receive Frame Sync Output Input I/O I/O I/O I/O 7 6384D-ATARM-04-May-09 Table 3-1. Signal Name Signal Description List (Continued) Function Type Timer/Counter - TCx Active Level Comments TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O Serial Peripheral Interface - SPIx_ SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1-SPIx_NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select I/O I/O I/O I/O Output Low Low Two-Wire Interface TWD TWCK Two-wire Serial Data Two-wire Serial Clock USB Host Port HDPA HDMA HDPB HDMB USB Host Port A Data + USB Host Port A Data USB Host Port B Data + USB Host Port B Data USB Device Port DDM DDP USB Device Port Data USB Device Port Data + Ethernet 10/100 ETXCK ERXCK ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO Transmit Clock or Reference Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Receive Data Receive Error Carrier Sense and Data Valid Collision Detect Management Data Clock Management Data Input/Output Input Input Output Output Output Input Input Input Input Input Output I/O MII only MII only ETX0-ETX1 only in RMII MII only RXDV in MII, CRSDV in RMII ERX0-ERX1 only in RMII MII only, REFCK in RMII MII only Analog Analog Analog Analog Analog Analog I/O I/O 8 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 3-1. Signal Name Signal Description List (Continued) Function Type Image Sensor Interface Active Level Comments ISI_D0-ISI_D11 ISI_MCK ISI_HSYNC ISI_VSYNC ISI_PCK Image Sensor Data Image Sensor Reference Clock Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data clock Input Output Input Input Input Analog to Digital Converter AD0-AD3 ADVREF ADTRG Note: Analog Inputs Analog Positive Reference ADC Trigger No PLLRCA line present on the AT91SAM9G20. Analog Analog Input Digital pulled-up inputs at reset 4. Package and Pinout * The AT91SAM9G20 is available in a 217-ball, 15 x 15 mm, LFBGA package (0.8 mm pitch) (Figure 4-1). * The AT91SAM9G20 is available in a 247-ball, 10 x 10 x 1.1 mm, TFBGA Green package, (0.5 mm pitch) (Figure 4-1). 4.1 217-ball LFBGA Package Outline Figure 4-1 shows the orientation of the 217-ball LFBGA package. A detailed mechanical description is given in the section "AT91SAM9G20 Mechanical Characteristics" of the product datasheet. Figure 4-1. 217-ball LFBGA Package (Top View) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGH J K LMNPRTU Ball A1 9 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 4.2 Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 217-ball LFBGA Pinout Pinout for 217-ball LFBGA Package Signal Name CFIOW/NBS3/NWR3 NBS0/A0 NWR2/NBS2/A1 A6 A8 A11 A13 BA0/A16 A18 A21 A22 CFWE/NWE/NWR0 CFOE/NRD NCS0 PC5 PC6 PC4 SDCK CFIOR/NBS1/NWR1 SDCS/NCS1 SDA10 A3 A7 A12 A15 A20 NANDWE PC7 PC10 PC13 PC11 PC14 PC8 WKUP D8 D1 CAS A2 A4 A9 A14 BA1/A17 A19 NANDOE PC9 PC12 DDP HDMB NC VDDUSB SHDN D9 D2 RAS D0 Table 4-1. Pin D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E14 E15 E16 E17 F1 F2 F3 F4 F14 F15 F16 F17 G1 G2 G3 G4 G14 G15 G16 G17 H1 H2 H3 H4 H8 H9 H10 H14 H15 H16 H17 J1 J2 J3 J4 J8 J9 J10 Signal Name A5 GND A10 GND VDDCORE GNDUSB VDDIOM GNDUSB DDM HDPB NC VDDBU XIN32 D10 D5 D3 D4 HDPA HDMA GNDBU XOUT32 D13 SDWE D6 GND OSCSEL BMS JTAGSEL TST PC15 D7 SDCKE VDDIOM GND NRST RTCK TMS PC18 D14 D12 D11 GND GND GND VDDCORE TCK NTRST PB18 PC19 PC17 VDDIOM PC16 GND GND GND Pin J14 J15 J16 J17 K1 K2 K3 K4 K8 K9 K10 K14 K15 K16 K17 L1 L2 L3 L4 L14 L15 L16 L17 M1 M2 M3 M4 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 Signal Name TDO PB19 TDI PB16 PC24 PC20 D15 PC21 GND GND GND PB4 PB17 GND PB15 GND PC26 PC25 VDDOSC PA28 PB9 PB8 PB14 VDDCORE PC31 GND PC22 PB1 PB2 PB3 PB7 XIN VDDPLL PC23 PC27 PA31 PA30 PB0 PB6 XOUT VDDPLL PC30 PC28 PB11 PB13 PB24 VDDIOP PB30 PB31 PA1 PA3 PA7 PA9 PA26 PA25 Pin P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name PB5 NC GNDANA PC29 VDDANA PB12 PB23 GND PB26 PB28 PA0 PA4 PA5 PA10 PA21 PA23 PA24 PA29 NC GNDPLL PC0 PC1 PB10 PB22 GND PB29 PA2 PA6 PA8 PA11 VDDCORE PA20 GND PA22 PA27 GNDPLL ADVREF PC2 PC3 PB20 PB21 PB25 PB27 PA12 PA13 PA14 PA15 PA19 PA17 PA16 PA18 VDDIOP 10 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 4.3 247-ball TFBGA Package Outline Figure 4-2 shows the orientation of the 247-ball TFBGA package. A detailed mechanical description is given in the section "AT91SAM9G20 Mechanical Characteristics" of the product datasheet. Figure 4-2. 247-ball TFBGA Package (Top View) Ball A1 1 A B C D E F G H J K L M N P R T U V W 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 11 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 4.4 Pin A1 A2 A12 A14 A16 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B13 B15 B17 B19 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C14 C16 C18 D2 D3 D13 D15 D17 D19 E2 E3 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E18 E19 F2 F3 F5 F6 247-ball TFBGA Package Pinout Pinout for 247-ball TFBGA Package Signal Name D13 D12 A9 A13 A20 A22 NANDOE D15 D14 D10 D9 D7 D3 D2 RAS CAS NWR2/NBS2/A1 A3 A10 A18 A21 VDDUSB PC15 D11 D8 SDCKE SDWE SDCK D1 SDCS/NCS1 A2 A7 A11 A19 GNDUSB CFWE/NWE/NWR0 PC17 PC16 A14 NANDWE CFOE/NRD NCS0 PC18 PC19 D6 D5 D0 CFIOW/NBS3/NWR3 GND A4 A8 VDDIOM BA0/A16 PC8 PC4 PC5 PC7 PC6 PC22 PC23 PC20 D4 Table 4-2. Pin F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 G2 G3 G5 G6 G8 G9 G10 G11 G12 G14 G15 G17 G18 H2 H3 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H17 H18 J2 J3 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J17 J18 K2 K3 K5 K6 K7 K8 K9 Signal Name CFIOR/NBS1/NWR1 SDA10 NBS0/A0 A6 A12 A15 BA1/A17 PC10 PC14 VDDUSB PC9 PC12 PC26 PC25 PC24 PC21 VDDCORE A5 VDDCORE VDDCORE VDDCORE PC13 GND GNDUSB PC11 PC31 PC30 PC28 PC27 PC29 GND GND VDDIOM VDDIOM GND VDDCORE SHDW VDDBU HDPB HDMB VDDOSC VDDPLL XOUT XIN VDDPLL GND VDDIOM VDDIOM VDDIOM GND GND WKUP DDP DDM VDDIOP GNDPLL GND NC GNDPLL VDDANA GND GND Pin K10 K11 K12 K13 K14 K15 K17 K18 L2 L3 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L17 L18 M2 M3 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M17 M18 N2 N3 N5 N6 N8 N11 N12 N14 N15 N17 N18 P2 P3 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 Signal Name GND VDDIOM GND GND XOUT32 XIN32 HDPA HDMA NC NC ADVREF PC2 GND GND GND GND VDDCORE GND OSCSEL GNDBU GND NRST TCK PC0 PC1 PC3 NTRST GND GND GND PA16 VDDCORE GND VDDIOP TST JTAGSEL PB18 TMS PB20 PB13 PB11 BMS GND PA17 PA23 GND VDDIOP TDO TDI PB24 PB22 GND GND PA6 PA7 PA11 GND PA18 PA24 PA28 PB3 PB5 Pin P17 P18 R2 R3 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R17 R18 T2 T3 T17 T18 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W18 W19 Signal Name RTCK PB16 GND PB29 PB26 PB27 PA5 GND PA12 GND PA19 PA26 PB1 GND PB7 PB14 PB9 PA1 PB10 PB19 PB17 GNDANA PB21 PB28 PB31 PA4 PA3 PA9 GND PA15 PA21 PA25 PA29 PA27 PA31 GND PB2 GND PB12 PB23 PB30 PA2 PA8 PA10 PA13 VDDIOP PA14 VDDIOP PA20 PA22 VDDIOP PA30 PB0 GND PB4 GND PB6 PB25 PA0 PB8 PB15 12 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 5. Power Considerations 5.1 Power Supplies The AT91SAM9G20 has several types of power supply pins: * VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V nominal. * VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V nominal). The voltage range is selectable by software. * VDDIOP pins: Power the Peripherals I/O lines; voltage ranges from 1.65V to 3.6V. * VDDBU pin: Powers the Slow Clock oscillator, the internal RC oscillator and a part of the System Controller; voltage ranges from 0.9V to 1.1V, 1.0V nominal. * VDDPLL pin: Powers the PLL cells; voltage ranges from 0.9V to 1.1V. * VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 1.65V to 3.6V * VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V to 3.6V, 3.3V nominal. * VDDUSB pin: Powers USB transceiver; voltage ranges from 3.0V to 3.6V. Ground pins GND are common to VDDCORE, VDDIOM, VDDOSC and VDDIOP pins power supplies. Separated ground pins are provided for VDDBU, VDDPLL, VDDUSB and VDDANA. These ground pins are respectively GNDBU, GNDPLL, GNDUSB and GNDANA. 5.2 Power Consumption The AT91SAM9G20 consumes about 4 mA of static current on VDDCORE at 25C. This static current rises at up to 18 mA if the temperature increases to 85C. On VDDBU, the current does not exceed 9 A at 25C. This static current rises at up to 18 A if the temperature increases to 85C. For dynamic power consumption, the AT91SAM9G20 consumes a maximum of 50 mA on VDDCORE at maximum conditions (1.0V, 25C, rises to 80mA at 85C, processor running fullperformance algorithm out of high-speed memories). 5.3 Programmable I/O Lines The power supplies pins VDDIOM accept two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories. The maximum speed is 133 MHz on the pin SDCK (SDRAM Clock) loaded with 10 pF. The other signals (control, address and data signals) do not go over 66 MHz, loaded with 30 pF for power supply at 1.8V and 50 pF for power supply at 3.3V. The EBI I/Os accept two slew rate modes, Fast and Slow. This allows to adapt the rising and falling time on SDRAM clock, control and data to the bus load. The voltage ranges and the slew rates are determined by programming VDDIOMSEL and IOSR bits in the Chip Configuration registers located in the Matrix User Interface. At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either 1.8V or 3.3V. The user must make sure to program the EBI voltage range before getting the device out of its Slow Clock Mode. At reset, the selected slew rates defaults are Fast. 13 6384D-ATARM-04-May-09 6. I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 k to GND, so that it can be left unconnected for normal operations. The NTRST signal is described in the Reset Pins paragraph. All the JTAG signals are supplied with VDDIOP. 6.2 Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 k to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. This pin is supplied with VDDBU. 6.3 Reset Pins NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP. NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor. As the product integrates power-on reset cells, which manages the processor and the JTAG reset, the NRST and NTRST pins can be left unconnected. The NRST and NTRST pins both integrate a permanent pull-up resistor of 100 k minimum to VDDIOP. The NRST signal is inserted in the Boundary Scan. 6.4 PIO Controllers All the I/O lines are Schmitt trigger inputs and all the lines managed by the PIO Controllers integrate a programmable pull-up resistor of 75 k typical with the exception of P4 - P31. For details, refer to the section "AT91SAM9G20 Electrical Characteristics". Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. 6.5 I/O Line Drive Levels The PIO lines drive current capability is described in the DC Characteristics section of the product datasheet. 6.6 Shutdown Logic Pins The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is no internal pull-up. An external pull-up to VDDBU is needed and its value must be higher than 1 M. The resistor value is calculated according to the regulator enable implementation and the SHDN level. 14 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. 6.7 Slow Clock Selection The AT91SAM9G20 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. 7. Processor and Architecture 7.1 ARM926EJ-S Processor * RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration * Two Instruction Sets - ARM High-performance 32-bit Instruction Set - Thumb High Code Density 16-bit Instruction Set * DSP Instruction Extensions * 5-Stage Pipeline Architecture: - Instruction Fetch (F) - Instruction Decode (D) - Execute (E) - Data Memory (M) - Register Write (W) * 32-Kbyte Data Cache, 32-Kbyte Instruction Cache - Virtually-addressed 4-way Associative Cache - Eight words per line - Write-through and Write-back Operation - Pseudo-random or Round-robin Replacement * Write Buffer - Main Write Buffer with 16-word Data Buffer and 4-address Buffer - DCache Write-back Buffer with 8-word Entries and a Single Address Entry - Software Control Drain * Standard ARM v4 and v5 Memory Management Unit (MMU) - Access Permission for Sections - Access Permission for large pages and small pages can be specified separately for each quarter of the page - 16 embedded domains * Bus Interface Unit (BIU) - Arbitrates and Schedules AHB Requests - Separate Masters for both instruction and data access providing complete Matrix system flexibility - Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface 15 6384D-ATARM-04-May-09 - On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words) 7.2 Bus Matrix * 6-layer Matrix, handling requests from 6 masters * Programmable Arbitration strategy - Fixed-priority Arbitration - Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master * Burst Management - Breaking with Slot Cycle Limit Support - Undefined Burst Length Support * One Address Decoder provided per Master - Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap * Boot Mode Select - Non-volatile Boot Memory can be internal or external - Selection is made by BMS pin sampled at reset * Remap Command - Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory * Allows Handling of Dynamic Exception Vectors 7.2.1 Matrix Masters The Bus Matrix of the AT91SAM9G20 manages six Masters, which means that each master can perform an access concurrently with others, according the slave it accesses is available. Each Master has its own decoder that can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. Table 7-1. Master 0 Master 1 Master 2 Master 3 Master 4 Master 5 List of Bus Matrix Masters ARM926TM Instruction ARM926 Data PDC ISI Controller Ethernet MAC USB Host DMA 7.2.2 Matrix Slaves Each Slave has its own arbiter, thus allowing to program a different arbitration per Slave. Table 7-2. Slave 0 Slave 1 List of Bus Matrix Slaves Internal SRAM0 16 KBytes Internal SRAM1 16 KBytes 16 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 7-2. Slave 2 Slave 3 Slave 4 List of Bus Matrix Slaves (Continued) Internal ROM USB Host User Interface External Bus Interface Internal Peripherals 7.2.3 Masters to Slaves Access All the Masters can normally access all the Slaves. However, some paths do not make sense, like as example allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown "-" in Table 7-3. Table 7-3. AT91SAM9G20 Masters to Slaves Access Master Slave Internal SRAM 16 Kbytes Internal SRAM 16 Kbytes Internal ROM 2 UHP User Interface 3 4 External Bus Interface Internal Peripherals X X X X X X X X X 0&1 ARM926 Instruction & Data X X X 2 Peripheral DMA Controller X X X 3 ISI Controller X X 4 Ethernet MAC X X 5 USB Host Controller X X - 0 1 7.3 Peripheral DMA Controller * Acting as one Matrix Master * Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. * Next Pointer Support, forbids strong real-time constraints on buffer management. * Twenty-four channels - Two for each USART - Two for the Debug Unit - Two for the Serial Synchronous Controller - Two for each Serial Peripheral Interface - One for Multimedia Card Interface - One for Analog-to-Digital Converter - Two for the Two-wire Interface The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): - TWI Transmit Channel - DBGU Transmit Channel - USART5 Transmit Channel 17 6384D-ATARM-04-May-09 - USART4 Transmit Channel - USART3 Transmit Channel - USART2 Transmit Channel - USART1 Transmit Channel - USART0 Transmit Channel - SPI1 Transmit Channel - SPI0 Transmit Channel - SSC Transmit Channel - TWI Receive Channel - DBGU Receive Channel - USART5 Receive Channel - USART4 Receive Channel - USART3 Receive Channel - USART2 Receive Channel - USART1 Receive Channel - USART0 Receive Channel - ADC Receive Channel - SPI1 Receive Channel - SPI0 Receive Channel - SSC Receive Channel - MCI Transmit/Receive Channel 7.4 Debug and Test Features * ARM926 Real-time In-circuit Emulator - Two real-time Watchpoint Units - Two Independent Registers: Debug Control Register and Debug Status Register - Test Access Port Accessible through JTAG Protocol - Debug Communications Channel * Debug Unit - Two-pin UART - Debug Communication Channel Interrupt Handling - Chip ID Register * IEEE1149.1 JTAG Boundary-scan on All Digital Pins 18 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 8. Memories Figure 8-1. AT91SAM9G20 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF Internal Memory Mapping 0x0000 0000 Boot Memory (1) Notes : (1) Can be ROM, EBI_NCS0 or SRAM depending on BMS and REMAP 256M Bytes 0x10 0000 ROM 0x10 8000 Reserved 32K Bytes 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 256M Bytes 0x20 0000 SRAM0 0x20 4000 Reserved 16K Bytes 0x2000 0000 EBI Chip Select 1/ SDRAMC 256M Bytes 0x30 0000 SRAM1 0x30 4000 Reserved 0x50 0000 16K Bytes 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 256M Bytes UHP 0x50 4000 Reserved 16K Bytes 0x4000 0000 EBI Chip Select 3/ NANDFlash EBI Chip Select 4/ Compact Flash Slot 0 EBI Chip Select 5/ Compact Flash Slot 1 EBI Chip Select 6 256M Bytes 0x0FFF FFFF 0x4FFF FFFF 0x5000 0000 256M Bytes 0x5FFF FFFF 0x6000 0000 Peripheral Mapping 256M Bytes 0xF000 0000 0x6FFF FFFF 0x7000 0000 256M Bytes Reserved 0xFFFA 0000 TCO, TC1, TC2 0xFFFA 4000 UDP 0xFFFA 8000 16K Bytes 16K Bytes System Controller Mapping 0xFFFF C000 Reserved 0xFFFF E800 ECC 512 Bytes 0x7FFF FFFF 0x8000 0000 EBI Chip Select 7 0x8FFF FFFF 256M Bytes 0xFFFA C000 MCI TWI 0xFFFB 0000 USART0 0xFFFB 4000 USART1 0xFFFB 8000 USART2 0xFFFB C000 SSC 0xFFFC 0000 ISI 0xFFFC 4000 EMAC 0xFFFC 8000 16K Bytes 16K Bytes 0xFFFF EA00 SDRAMC 0xFFFF EC00 512 Bytes 0x9000 0000 16K Bytes 0xFFFF EE00 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF F600 16K Bytes 16K Bytes 0xFFFF F800 SMC MATRIX 0xFFFF EF10 0xFFFF F000 CCFG AIC 0xFFFF F200 DBGU 0xFFFF F400 PIOA 512 Bytes 512 Bytes 512 Bytes 512 Bytes 512 Bytes Undefined (Abort) 1,518M Bytes 0xFFFC C000 SPI0 PIOB 512 bytes SPI1 0xFFFD 0000 USART3 0xFFFD 4000 USART4 0xFFFD 8000 USART5 0xFFFD C000 TC3, TC4, TC5 0xFFFE 0000 0xEFFF FFFF ADC 0xFFFE 4000 PIOC 16K Bytes 16K Bytes 16K Bytes 0xFFFF FA00 Reserved 0xFFFF FC00 PMC 0xFFFF FD00 RSTC 0xFFFF FD10 16K Bytes 16K Bytes 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 WDTC SHDC RTTC PITC 0xFFFF FD50 0xFFFF FD60 16K Bytes 0xFFFF FFFF 512 bytes 256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 0xF000 0000 Internal Peripherals 0xFFFF FFFF Reserved 256M Bytes 0xFFFF C000 SYSC 0xFFFF FFFF GPBR Reserved 19 6384D-ATARM-04-May-09 A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes. The banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. However, in order to simplify the mappings, all the masters have a similar address decoding. Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to Table 8-1, "Internal Memory Mapping," on page 20 for details. A complete memory map is presented in Figure 8-1 on page 19. 8.1 Embedded Memories * 64-KByte ROM - Single Cycle Access at full matrix speed * Two 16-Kbyte Fast SRAM - Single Cycle Access at full matrix speed 8.1.1 Boot Strategies Table 8-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the BMS state at reset. Table 8-1. Internal Memory Mapping REMAP = 0 Address BMS = 1 0x0000 0000 0x0010 0000 0x0020 0000 0x0030 0000 0x0050 0000 ROM BMS = 0 EBI_NCS0 ROM SRAM0 16K SRAM1 16K USB Host User Interface SRAM0 16K REMAP = 1 The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can be configured with two parameters. REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted. When REMAP = 1, BMS is ignored. Refer to the Bus Matrix Section for more details. 20 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 8-1 on page 19. The AT91SAM9G20 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. 8.1.1.1 BMS = 1, Boot on Embedded ROM The system boots using the Boot Program. * Boot on slow clock (On-chip RC or 32,768 Hz) * Auto baudrate detection * Downloads and runs an application from external storage media into internal SRAM * Downloaded code size depends on embedded SRAM size * Automatic detection of valid application * Bootloader on a non-volatile memory - SDCard (boot ROM does not support high capacity SDCards.) - NAND Flash - SPI DataFlash(R) and Serial Flash connected on NPCS0 and NPCS1 of the SPI0 - EEPROM on TWI * SAM-BA(R) Boot in case no valid program is detected in external NVM, supporting - Serial communication on a DBGU - USB Device HS Port 8.1.1.2 BMS = 0, Boot on External Memory * Boot on slow clock (On-chip RC or 32,768 Hz) * Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take the following steps: 1. Program the PMC (main oscillator enable or bypass mode). 2. Program and start the PLL. 3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock. 4. Switch the main clock to the new value. 8.2 External Memories The external memories are accessed through the External Bus Interface. Each Chip Select line has a 256-Mbyte memory area assigned. 21 6384D-ATARM-04-May-09 Refer to the memory map in Figure 8-1 on page 19. 8.2.1 External Bus Interface * Integrates three External Memory Controllers - Static Memory Controller - SDRAM Controller - ECC Controller * Additional logic for NAND Flash * Full 32-bit External Data Bus * Up to 26-bit Address Bus (up to 64MBytes linear) * Up to 8 chip selects, Configurable Assignment: - Static Memory Controller on NCS0 - SDRAM Controller or Static Memory Controller on NCS1 - Static Memory Controller on NCS2 - Static Memory Controller on NCS3, Optional NAND Flash support - Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support - Static Memory Controller on NCS6-NCS7 8.2.2 Static Memory Controller * 8-, 16- or 32-bit Data Bus * Multiple Access Modes supported - Byte Write or Byte Select Lines - Asynchronous read in Page Mode supported (4- up to 32-byte page size) * Multiple device adaptability - Compliant with LCD Module - Control signals programmable setup, pulse and hold time for each Memory Bank * Multiple Wait State Management - Programmable Wait State Generation - External Wait Request - Programmable Data Float Time * Slow Clock mode supported 8.2.3 SDRAM Controller * Supported devices - Standard and Low-power SDRAM (Mobile SDRAM) * Numerous configurations supported - 2K, 4K, 8K Row Address Memory Parts - SDRAM with two or four Internal Banks - SDRAM with 16- or 32-bit Datapath * Programming facilities - Word, half-word, byte access - Automatic page break when Memory Boundary has been reached 22 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary - Multibank Ping-pong Access - Timing parameters specified by software - Automatic refresh operation, refresh rate is programmable * Energy-saving capabilities - Self-refresh, power down and deep power down modes supported * Error detection - Refresh Error Interrupt * SDRAM Power-up Initialization by software * CAS Latency of 1, 2 and 3 supported * Auto Precharge Command not used 8.2.4 Error Corrected Code Controller * Hardware Error Corrected Code (ECC) Generation - Detection and Correction by Software * Supports NAND Flash and SmartMediaTM Devices with 8- or 16-bit Data Path. * Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes, Specified by Software * Supports 1 bit correction for a page of 512,1024,2048 and 4096 Bytes with 8- or 16-bit Data Path * Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 Bytes with 8-bit Data Path * Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 Bytes with 8-bit Data Path 9. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface embeds also the registers allowing to configure the Matrix and a set of registers for the chip configuration. The chip configuration registers allows configuring: - EBI chip select assignment and Voltage range for external memories The System Controller's peripherals are all mapped within the highest 16 Kbytes of address space, between addresses 0xFFFF E800 and 0xFFFF FFFF. However, all the registers of System Controller are mapped on the top of the address space. All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction has an indexing mode of 4 Kbytes. Figure 9-1 on page 24 shows the System Controller block diagram. Figure 8-1 on page 19 shows the mapping of the User Interfaces of the System Controller peripherals. 23 6384D-ATARM-04-May-09 9.1 System Controller Block Diagram AT91SAM9G20 System Controller Block Diagram System Controller VDDCORE Powered irq0-irq2 fiq periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC NRST VDDCORE POR por_ntrst jtag_nreset rstc_irq Reset Controller periph_nreset proc_nreset backup_nreset VDDBU Powered SLCK rtt_irq rtt_alarm UDPCK periph_clk[10] RC OSC SLOW CLOCK OSC SLCK int MAIN OSC PLLA PLLB MAINCK Power Management Controller Shut-Down Controller periph_nreset periph_irq[10] 4 General-Purpose Backup Registers USB Device Port UHPCK periph_clk[20] periph_nreset periph_irq[20] USB Host Port Debug Unit Advanced Interrupt Controller int por_ntrst ntrst ARM926EJ-S nirq nfiq Figure 9-1. dbgu_irq dbgu_txd pit_irq proc_nreset PCK debug jtag_nreset wdt_irq MCK periph_nreset Boundary Scan TAP Controller Bus Matrix VDDBU VDDBU POR SLCK backup_nreset SLCK SHDN WKUP backup_nreset rtt0_alarm OSCSEL XIN32 XOUT32 Real-Time Timer periph_clk[2..27] pck[0-1] PCK UDPCK UHPCK MCK XIN XOUT PLLACK PLLBCK periph_nreset pmc_irq idle periph_clk[6..24] periph_nreset periph_nreset periph_clk[2..4] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 PIO Controllers periph_irq[2..4] irq0-irq2 fiq dbgu_txd Embedded Peripherals periph_irq[6..24] in out enable 24 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 9.2 Reset Controller * Based on two Power-on-Reset cell - one on VDDBU and one on VDDCORE * Status of the last reset - Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset * Controls the internal resets and the NRST pin output - Allows shaping a reset signal for the external devices 9.3 Shutdown Controller * Shutdown and Wake-Up logic - Software programmable assertion of the SHDWN pin - Deassertion Programmable on a WKUP pin level change or on alarm 9.4 Clock Generator * Embeds a Low Power 32768 Hz Slow Clock Oscillator and a Low power RC oscillator selectable with OSCSEL signal - Provides the permanent Slow Clock SLCK to the system * Embeds the Main Oscillator - Oscillator bypass feature - Supports 3 to 20 MHz crystals * Embeds 2 PLLs - The PLL A outputs 400-800 MHz clock - The PLL B outputs 100 MHz clock - Both integrate an input divider to increase output accuracy - PLL A and PLL B embed their own filters 25 6384D-ATARM-04-May-09 Figure 9-2. Clock Generator Block Diagram Clock Generator OSCSEL On Chip RC OSC XIN32 XOUT32 XIN XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator Slow Clock SLCK PLL and Divider A PLL and Divider B PLLA Clock PLLACK PLLB Clock PLLBCK Status Control Power Management Controller 9.5 Power Management Controller * Provides: - the Processor Clock PCK - the Master Clock MCK, in particular to the Matrix and the memory interfaces.The MCK divider can be 1,2,4,6 - the USB Device Clock UDPCK - independent peripheral clocks, typically at the frequency of MCK - 2 programmable clock outputs: PCK0, PCK1 * Five flexible operating modes: - Normal Mode, processor and peripherals running at a programmable frequency - Idle Mode, processor stopped waiting for an interrupt - Slow Clock Mode, processor and peripherals running at low frequency - Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt - Backup Mode, Main Power Supplies off, VDDBU powered by a battery 26 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 9-3. AT91SAM9G20 Power Management Controller Block Diagram Divider /1,/2 Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,.../64 Divider /1,/2,/4,/6 Peripherals Clock Controller ON/OFF Processor Clock Controller Idle Mode PCK int MCK periph_clk[..] Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] USB Clock Controller PLLBCK Divider /1,/2,/4 ON/OFF UDPCK 9.6 Periodic Interval Timer * Includes a 20-bit Periodic Counter, with less than 1 s accuracy * Includes a 12-bit Interval Overlay Counter * Real Time OS or Linux(R)/Windows CE(R) compliant tick generator 9.7 Watchdog Timer * 16-bit key-protected only-once-Programmable Counter * Windowed, prevents the processor being in a dead-lock on the watchdog access 9.8 Real-time Timer * Real-time Timer 32-bit free-running back-up Counter * Integrates a 16-bit programmable prescaler running on slow clock * Alarm Register capable of generating a wake-up of the system through the Shutdown Controller 9.9 General-purpose Back-up Registers * Four 32-bit backup general-purpose registers 9.10 Advanced Interrupt Controller * Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor * Thirty-two individually maskable and vectored interrupt sources 27 6384D-ATARM-04-May-09 - Source 0 is reserved for the Fast Interrupt Input (FIQ) - Source 1 is reserved for system peripherals - Programmable Edge-triggered or Level-sensitive Internal Sources - Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive * Three External Sources plus the Fast Interrupt signal * 8-level Priority Controller - Drives the Normal Interrupt of the processor - Handles priority of the interrupt sources 1 to 31 - Higher priority interrupts can be served during service of lower priority interrupt * Vectoring - Optimizes Interrupt Service Routine Branch and Execution - One 32-bit Vector Register per interrupt source - Interrupt Vector Register reads the corresponding current Interrupt Vector * Protect Mode - Easy debugging by preventing automatic operations when protect models are enabled * Fast Forcing - Permits redirecting any normal interrupt source on the Fast Interrupt of the processor 9.11 Debug Unit * Composed of two functions: - Two-pin UART - Debug Communication Channel (DCC) support * Two-pin UART - Implemented features are 100% compatible with the standard Atmel (R) USART - Independent receiver and transmitter with a common programmable Baud Rate Generator - Even, Odd, Mark or Space Parity Generation - Parity, Framing and Overrun Error Detection - Automatic Echo, Local Loopback and Remote Loopback Channel Modes - Support for two PDC channels with connection to receiver and transmitter * Debug Communication Channel Support - Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor's ICE Interface 9.12 Chip Identification * Chip ID:0x019905A1 * JTAG ID: 0x05B2403F * ARM926 TAP ID:0x0792603F 28 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 10. Peripherals 10.1 User Interface The peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 19. 10.2 Identifiers Table 10-1 defines the Peripheral Identifiers of the AT91SAM9G20. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 AT91SAM9G20 Peripheral Identifiers (Continued) Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC ADC US0 US1 US2 MCI UDP TWI SPI0 SPI1 SSC TC0 TC1 TC2 UHP EMAC ISI US3 US4 US5 TC3 TC4 TC5 Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A Parallel I/O Controller B Parallel I/O Controller C Analog to Digital Converter USART 0 USART 1 USART 2 Multimedia Card Interface USB Device Port Two-wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller Reserved Reserved Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 USB Host Port Ethernet MAC Image Sensor Interface USART 3 USART 4 USART 5 Timer/Counter 3 Timer/Counter 4 Timer/Counter 5 External Interrupt FIQ 29 6384D-ATARM-04-May-09 Table 10-1. Peripheral ID 29 30 31 AT91SAM9G20 Peripheral Identifiers (Continued) Peripheral Mnemonic AIC AIC AIC Peripheral Name Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller External Interrupt IRQ0 IRQ1 IRQ2 Note: Setting AIC, SYSC, UHP, ADC and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. The ADC clock is automatically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion. 10.2.1 10.2.1.1 Peripheral Interrupts and Clock Control System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: * the SDRAM Controller * the Debug Unit * the Periodic Interval Timer * the Real-time Timer * the Watchdog Timer * the Reset Controller * the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.2.1.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.3 Peripheral Signal Multiplexing on I/O Lines The AT91SAM9G20 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. Table 10-2 on page 31, Table 10-3 on page 32 and Table 10-4 on page 33 define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns "Function" and "Comments" have been inserted in this table for the user's own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions which are output only might be duplicated within both tables. The column "Reset State" indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O appears, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name appears in the "Reset State" column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 30 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 10.3.1 PIO Controller A Multiplexing Multiplexing on PIO Controller A PIO Controller A I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 RTS2 CTS2 MCDA0 MCCDA MCCK MCDA1 MCDA2 MCDA3 ETX0 ETX1 ERX0 ERX1 ETXEN ERXDV ERXER ETXCK EMDC EMDIO ADTRG TWD TWCK TCLK0 TIOA0 TIOA1 TIOA2 SCK1 SCK2 SCK0 ETXER ETX2 ETX3 ERX2 ERX3 ERXCK ECRS ECOL RXD4 TXD4 ETX2 ETX3 MCDB3 MCDB2 MCDB1 Peripheral B MCDB0 MCCDB Comments Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Application Usage Power Supply VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Function Comments Table 10-2. 31 6384D-ATARM-04-May-09 10.3.2 PIO Controller B Multiplexing Multiplexing on PIO Controller B PIO Controller B Application Usage Comments Reset State I/O I/O I/O I/O I/O I/O TCLK1 TCLK2 I/O I/O I/O I/O ISI_D8 ISI_D9 ISI_D10 ISI_D11 I/O I/O I/O I/O I/O I/O TCLK3 TCLK4 TIOB4 TIOB5 ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_VSYNC ISI_HSYNC ISI_MCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Function Comments Table 10-3. I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Peripheral A SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 TXD3 RXD3 TXD5 RXD5 DRXD DTXD TK0 TF0 TD0 RD0 RK0 RF0 DSR0 DCD0 DTR0 RI0 RTS0 CTS0 RTS1 CTS1 PCK0 PCK1 Peripheral B TIOA3 TIOB3 TIOA4 TIOA5 32 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 10.3.3 PIO Controller C Multiplexing Multiplexing on PIO Controller C PIO Controller C I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 A23 A24 TIOB2 TIOB1 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW NCS2 IRQ0 FIQ NCS3/NANDCS NWAIT D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 TCLK5 Peripheral A Peripheral B SCK3 PCK0 PCK1 SPI1_NPCS3 SPI1_NPCS2 SPI1_NPCS1 CFCE1 CFCE2 RTS3 TIOB0 CTS3 SPI0_NPCS1 NCS7 NCS6 IRQ2 IRQ1 SPI0_NPCS2 SPI0_NPCS3 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 Comments AD0 AD1 AD2 AD3 Reset State I/O I/O I/O I/O A23 A24 I/O I/O I/O I/O A25 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Application Usage Power Supply VDDANA VDDANA VDDANA VDDANA VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Function Comments Table 10-4. 33 6384D-ATARM-04-May-09 10.4 10.4.1 Embedded Peripherals Serial Peripheral Interface * Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to 15 peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors * Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection * Very fast transfers supported - Transfers with baud rates up to MCK - The chip select line may be left active to speed up transfers on the same device 10.4.2 Two-wire Interface * Compatibility with standard two-wire serial memory * One, two or three bytes for slave address * Sequential read/write operations * Supports either master or slave modes * Compatible with standard two-wire serial memories * Master, multi-master and slave mode operation * Bit rate: up to 400 Kbits * General Call supported in slave mode * Connection to Peripheral DMA Controller (PDC) capabilities optimizes data transfers in master mode only - One channel for the receiver, one channel for the transmitter - Next buffer support 10.4.3 USART * Programmable Baud Rate Generator * 5- to 9-bit full-duplex synchronous or asynchronous serial communications - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode - Parity generation and error detection - Framing error detection, overrun error detection - MSB- or LSB-first - Optional break generation and detection 34 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary - By 8 or by-16 over-sampling receiver frequency - Hardware handshaking RTS-CTS - Optional modem signal management DTR-DSR-DCD-RI - Receiver time-out and transmitter timeguard - Optional Multi-drop Mode with address generation and detection - Optional Manchester Encoding * RS485 with driver control signal * ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit * IrDA modulation and demodulation - Communication at up to 115.2 Kbps * Test Modes - Remote Loopback, Local Loopback, Automatic Echo The USART contains features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the AT91SAM9G20, only the USART0 implements these signals, named DTR0, DSR0, DCD0 and RI0. The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1 and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features. Thus, programming the USART1, USART2 or the USART3 in Modem Mode may lead to unpredictable results. In these USARTs, the commands relating to the Modem Mode have no effect and the status bits relating the status of the modem signals are never activated. 10.4.4 Serial Synchronous Controller * Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.) * Contains an independent receiver and transmitter and a common clock divider * Offers a configurable frame sync and data length * Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal * Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.4.5 Timer Counter * Two blocks of three 16-bit Timer Counter channels * Each channel can be individually programmed to perform a wide range of functions including: - Frequency Measurement - Event Counting - Interval Measurement - Pulse Generation - Delay Timing - Pulse Width Modulation - Up/down Capabilities * Each channel is user-configurable and contains: 35 6384D-ATARM-04-May-09 - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals * Each block contains two global registers that act on all three TC Channels Note: TC Block 0 (TC0, TC1, TC2) and TC Block 1 (TC3, TC4, TC5) have identical user interfaces. See Figure 8-1, "AT91SAM9G20 Memory Mapping," on page 19 for TC Block 0 and TC Block 1 base addresses. 10.4.6 Multimedia Card Interface * One double-channel MultiMedia Card Interface * Compatibility with MultiMedia Card Specification Version 3.11 * Compatibility with SD Memory Card Specification Version 1.1 * Compatibility with SDIO Specification Version V1.0. * Card clock rate up to Master Clock divided by 2 * Embedded power management to slow down clock rate when not used * MCI has two slots, each supporting - One slot for one MultiMediaCard bus (up to 30 cards) or - One SD Memory Card * Support for stream, block and multi-block data read and write 10.4.7 USB Host Port * Compliance with Open HCI Rev 1.0 Specification * Compliance with USB V2.0 Full-speed and Low-speed Specification * Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices * Root hub integrated with two downstream USB ports in the 217-LFBGA package * Two embedded USB transceivers * Supports power management * Operates as a master on the Matrix 10.4.8 USB Device Port * USB V2.0 full-speed compliant, 12 MBits per second * Embedded USB V2.0 full-speed transceiver * Embedded 2,432-byte dual-port RAM for endpoints * Suspend/Resume logic * Ping-pong mode (two memory banks) for isochronous and bulk endpoints * Six general-purpose endpoints - Endpoint 0 and 3: 64 bytes, no ping-pong mode - Endpoint 1 and 2: 64 bytes, ping-pong mode - Endpoint 4 and 5: 512 bytes, ping-pong mode * Embedded pad pull-up 10.4.9 Ethernet 10/100 MAC * Compatibility with IEEE Standard 802.3 36 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * 10 and 100 MBits per second data throughput capability * Full- and half-duplex operations * MII or RMII interface to the physical layer * Register Interface to address, data, status and control registers * DMA Interface, operating as a master on the Memory Controller * Interrupt generation to signal receive and transmit completion * 28-byte transmit and 28-byte receive FIFOs * Automatic pad and CRC generation on transmitted frames * Address checking logic to recognize four 48-bit addresses * Support promiscuous mode where all valid frames are copied to memory * Support physical layer management through MDIO interface 10.4.10 Image Sensor Interface * ITU-R BT. 601/656 8-bit mode external interface support * Support for ITU-R BT.656-4 SAV and EAV synchronization * Vertical and horizontal resolutions up to 2048 x 2048 * Preview Path up to 640 x 480 in RGMB mode, 2048 x2048 in grayscale mode * Support for packed data formatting for YCbCr 4:2:2 formats * Preview scaler to generate smaller size image * Programmable frame capture rate 10.4.11 Analog-to-Digital Converter * 4-channel ADC * 10-bit 312K samples/sec. Successive Approximation Register ADC * -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity * Individual enable and disable of each channel * External voltage reference for better accuracy on low voltage inputs * Multiple trigger source - Hardware or software trigger - External trigger pin - Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger * Sleep Mode and conversion sequencer - Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels * Four analog inputs shared with digital signals 37 6384D-ATARM-04-May-09 38 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 11. ARM926EJ-S Processor Overview 11.1 Overview The ARM926EJ-S processor is a member of the ARM9TM family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multitasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Javapowered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S provides a complete high performance processor subsystem, including: * an ARM9EJ-STM integer core * a Memory Management Unit (MMU) * separate instruction and data AMBA AHB bus interfaces * separate instruction and data TCM interfaces 39 6384D-ATARM-04-May-09 11.2 Block Diagram Figure 11-1. ARM926EJ-S Internal Functional Block Diagram External Coprocessors ETM9 CP15 System Configuration Coprocessor External Coprocessor Interface Trace Port Interface Write Data ARM9EJ-S Processor Core Instruction Fetches Read Data Data Address MMU Instruction Address DTCM Interface Data TLB Instruction TLB ITCM Interface Data TCM Instruction TCM Data Address Data Cache AHB Interface and Write Buffer Instruction Address Instruction Cache AMBA AHB 40 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 11.3 11.3.1 ARM9EJ-S Processor ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: * ARM state: 32-bit, word-aligned ARM instructions. * THUMB state: 16-bit, halfword-aligned Thumb instructions. * Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 11.3.2 Switching State The operating state of the ARM9EJ-S core can be switched between: * ARM state and THUMB state using the BX and BLX instructions, and loads to the PC * ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler. 11.3.3 Instruction Pipelines The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute, Memory and Writeback stages. A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages. 11.3.4 Memory Access The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these cases and stalls the core or forward data. 11.3.5 Jazelle Technology The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing high performance for the next generation of Java-powered wireless and embedded devices. The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode will appear as another state: instead of executing ARM or Thumb instructions, it executes Java byte codes. The Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. 41 6384D-ATARM-04-May-09 Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software. 11.3.6 ARM9EJ-S Operating Modes In all states, there are seven operation modes: * User mode is the usual ARM program execution state. It is used for executing most application programs * Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process * Interrupt (IRQ) mode is used for general-purpose interrupt handling * Supervisor mode is a protected mode for the operating system * Abort mode is entered after a data or instruction prefetch abort * System mode is a privileged user mode for the operating system * Undefined mode is entered when an undefined instruction exception occurs Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 11.3.7 ARM9EJ-S Registers The ARM9EJ-S core has a total of 37 registers. * 31 general-purpose 32-bit registers * 6 32-bit status registers Table 11-1 shows all the registers in all modes. Table 11-1. User and System Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 ARM9TDMI Modes and Registers Layout Supervisor Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 Abort Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 Undefined Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 Fast Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ 42 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 11-1. User and System Mode R12 R13 R14 PC ARM9TDMI Modes and Registers Layout (Continued) Supervisor Mode R12 R13_SVC R14_SVC PC Abort Mode R12 R13_ABORT R14_ABORT PC Undefined Mode R12 R13_UNDEF R14_UNDEF PC Interrupt Mode R12 R13_IRQ R14_IRQ PC Fast Interrupt Mode R12_FIQ R13_FIQ R14_FIQ PC CPSR CPSR SPSR_SVC CPSR SPSR_ABOR T CPSR SPSR_UNDE F CPSR SPSR_IRQ CPSR SPSR_FIQ Mode-specific banked registers The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits. In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines: * constraints on the use of registers * stack conventions * argument passing and result return For more details, refer to ARM Software Development Kit. The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: * Eight general-purpose registers r0-r7 * Stack pointer, SP * Link register, LR (ARM r14) * PC * CPSR 43 6384D-ATARM-04-May-09 There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S Technical Reference Manual, revision r1p2 page 2-12). 11.3.7.1 Status Registers The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: * hold information about the most recently performed ALU operation * control the enabling and disabling of interrupts * set the processor operation mode Figure 11-2. Status Register Format 31 30 29 28 27 24 765 0 NZCVQ J Reserved I FT Mode Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than Mode bits Thumb state bit FIQ disable IRQ disable Figure 11-2 shows the status register format, where: * N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags * The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag. * The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where: - J = 0: The processor is in ARM or Thumb state, depending on the T bit - J = 1: The processor is in Jazelle state. * Mode: five bits to encode the current processor mode 11.3.7.2 Exceptions Exception Types and Priorities The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi- leged mode. The types of exceptions are: * Fast interrupt (FIQ) * Normal interrupt (IRQ) * Data and Prefetched aborts (Abort) * Undefined instruction (Undefined) * Software interrupt and Reset (Supervisor) 44 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to the following priority order: * Reset (highest priority) * Data Abort * FIQ * IRQ * Prefetch Abort * BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. Exception Modes and Handling Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral. When handling an ARM exception, the ARM9EJ-S core performs the following operations: 1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from: - ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception). - THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. Copies the CPSR into the appropriate SPSR. 3. Forces the CPSR mode bits to a value that depends on the exception. 4. Forces the PC to fetch the next instruction from the relevant exception vector. The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR. The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the 45 6384D-ATARM-04-May-09 pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 11.3.8 ARM Instruction Set Overview The ARM instruction set is divided into: * Branch instructions * Data processing instructions * Status register transfer instructions * Load and Store instructions * Coprocessor instructions * Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). For further details, see the ARM Technical Reference Manual, ARM ref. DDI0198B. Table 11-2 gives the ARM instruction mnemonic list. Table 11-2. Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Mnemonic MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR Operation Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word 46 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 11-2. Mnemonic LDRH LDRB LDRBT LDRT LDM SWP MCR LDC CDP ARM Instruction Mnemonic List (Continued) Operation Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor Coprocessor Data Processing Mnemonic STRH STRB STRBT STRT STM SWPB MRC STC Operation Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor 11.3.9 New ARM Instruction Set . Table 11-3. Mnemonic BXJ BLX (1) SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB New ARM Instruction Mnemonic List Operation Branch and exchange to Java Branch, Link and exchange Signed Multiply Accumulate 16 * 16 bit Signed Multiply Accumulate Long Signed Multiply Accumulate 32 * 16 bit Signed Multiply 16 * 16 bit Signed Multiply 32 * 16 bit Saturated Add Saturated Add with Double Saturated subtract Saturated Subtract with double Mnemonic MRRC MCR2 MCRR CDP2 BKPT PLD STRD STC2 LDRD LDC2 CLZ Operation Move double from coprocessor Alternative move of ARM reg to coprocessor Move double to coprocessor Alternative Coprocessor Data Processing Breakpoint Soft Preload, Memory prepare to load from address Store Double Alternative Store from Coprocessor Load Double Alternative Load to Coprocessor Count Leading Zeroes Note: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. 11.3.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: * Branch instructions * Data processing instructions * Load and Store instructions * Load and Store multiple instructions 47 6384D-ATARM-04-May-09 * Exception-generating instruction Table 5 shows the Thumb instruction set, for further details, see the ARM Technical Reference Manual, ARM ref. DDI0198B. Table 11-4 gives the Thumb instruction mnemonic list. Table 11-4. Mnemonic MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Conditional Branch Mnemonic MVN ADC SBC CMN NEG BIC ORR LSR ROR BLX BL SWI STR STRH STRB LDRSB STMIA POP BKPT Operation Move Not Add with Carry Subtract with Carry Compare Negated Negate Bit Clear Logical (inclusive) OR Logical Shift Right Rotate Right Branch, Link, and Exchange Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack Breakpoint 48 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 11.4 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: * ARM9EJ-S * Caches (ICache, DCache and write buffer) * TCM * MMU * Other system options To control these features, CP15 provides 16 additional registers. See Table 11-5. Table 11-5. Register 0 0 0 1 2 3 4 5 5 6 7 8 9 9 10 11 12 13 13 14 15 Notes: CP15 Registers Name ID Code (1) (1) Read/Write Read/Unpredictable Read/Unpredictable Read/Unpredictable Read/write Read/write Read/write None (1) (1) Cache type TCM status(1) Control Translation Table Base Domain Access Control Reserved Data fault Status Read/write Read/write Read/write Read/Write Unpredictable/Write Instruction fault status Fault Address Cache Operations TLB operations cache lockdown TCM region TLB lockdown Reserved Reserved FCSE PID (1) (2) Read/write Read/write Read/write None None Read/write Read/Write None Read/Write Context ID(1) Reserved Test configuration 1. Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. 49 6384D-ATARM-04-May-09 11.4.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: * MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. * MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR, MRC instructions bit pattern is shown below: 31 30 29 28 27 26 25 24 cond 23 22 21 20 1 19 1 18 1 17 0 16 opcode_1 15 14 13 L 12 11 10 CRn 9 8 Rd 7 6 5 4 1 3 1 2 1 1 1 0 opcode_2 1 CRm * CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. * opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. * Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. * CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. * L: Instruction Bit 0 = MCR instruction 1 = MRC instruction * opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. * cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM. 50 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 11.5 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS(R), Windows CE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address. The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages. Table 7 shows the different attributes of each page in the physical memory. Table 11-6. Mapping Details Mapping Size 1M byte 64K bytes 4K bytes 1K byte Access Permission By Section 4 separated subpages 4 separated subpages Tiny Page Subpage Size 16K bytes 1K byte - Mapping Name Section Large Page Small Page Tiny Page The MMU consists of: * Access control logic * Translation Look-aside Buffer (TLB) * Translation table walk hardware 11.5.1 Access Control Logic The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored. The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). 11.5.2 Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- 51 6384D-ATARM-04-May-09 fied Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 11.5.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access. Pagemapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual. 11.5.4 MMU Faults The MMU generates an abort on the following types of faults: * Alignment faults (for data accesses only) * Translation faults * Domain faults * Permission faults The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register. The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual. 52 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 11.6 Caches and Write Buffer The ARM926EJ-S contains a 32 KB Instruction Cache (ICache), a 32 KB Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and CP15 register 9 (cache lockdown). 11.6.1 Instruction Cache (ICache) The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 11.6.2 Data Cache (DCache) and Write Buffer ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected. DCache The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating every time a context switch occurs. The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations. Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the 53 6384D-ATARM-04-May-09 11.6.2.1 cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. 11.6.2.2 Write Buffer The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and write-back region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks. DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables. 11.6.2.3 Write-though Operation When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 11.6.2.4 Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 54 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 11.7 Bus Interface Unit The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits: * It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. * Each AHB layer becomes simple because it only has one master, so no arbitration or masterto-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. * The arbitration becomes effective when more than one master wants to access the same slave simultaneously. 11.7.1 Supported Transfers The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. Table 8 gives an overview of the supported transfers and different kinds of transactions they are used for. Table 11-7. HBurst[2:0] Supported Transfers Description Single transfer of word, half word, or byte: * data write (NCNB, NCB, WT, or WB that has missed in DCache) SINGLE Single transfer * data read (NCNB or NCB) * NC instruction fetch (prefetched and non-prefetched) * page table walk read Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT, or WB write. Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write. Cache linefill INCR4 INCR8 WRAP8 Four-word incrementing burst Eight-word incrementing burst Eight-word wrapping burst 11.7.2 Thumb Instruction Fetches All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time. Address Alignment The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. 11.7.3 55 6384D-ATARM-04-May-09 56 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 12. AT91SAM9G20 Debug and Test 12.1 Overview The AT91SAM9G20 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 57 6384D-ATARM-04-May-09 12.2 Block Diagram Figure 12-1. Debug and Test Block Diagram TMS TCK TDI NTRST Boundary Port ICE/JTAG TAP JTAGSEL TDO RTCK Reset and Test POR TST ARM9EJ-S ICE-RT ARM926EJ-S PDC DBGU PIO DTXD DRXD TAP: Test Access Port 58 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 12.3 12.3.1 Application Examples Debug Environment Figure 12-2 on page 59 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 12-2. Application Debug and Trace Environment Example Host Debugger ICE/JTA ICE/JTAG AT91SAM9G20 RS232 Connector Terminal AT91SAM9G20-based Application 59 6384D-ATARM-04-May-09 12.3.2 Test Environment Figure 12-3 on page 60 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the "board in test" is designed using a number of JTAGcompliant devices. These devices can be connected to form a single scan chain. Figure 12-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n Chip 2 AT91SAM9G20 Chip 1 AT91SAM9G20-based Application Board In Test 12.4 Debug and Test Pin Description Table 12-1. Pin Name Debug and Test Pin List Function Reset/Test Type Active Level NRST TST Microcontroller Reset Test Mode Select ICE and JTAG Input/Output Input Low High NTRST TCK TDI TDO TMS RTCK JTAGSEL Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select Returned Test Clock JTAG Selection Debug Unit Input Input Input Output Input Output Input Low DRXD DTXD Debug Receive Data Debug Transmit Data Input Output 60 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 12.5 12.5.1 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 12.5.2 EmbeddedICE The ARM9EJ-S EmbeddedICE-RTTM is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port. EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the EmbeddedICE-RT, see the ARM document: ARM9EJ-S Technical Reference Manual (DDI 0222A). 12.5.3 JTAG Signal Description TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9ETM running from the 32.768 kHz slow clock. RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators. From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. 61 6384D-ATARM-04-May-09 12.5.4 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM9G20 Debug Unit Chip ID value is 0x0199 05A1 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. 12.5.5 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 12.5.5.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 308 bits that correspond to active pins and associated control signals. Each AT91SAM9G20 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 12-2. Bit Number 307 A0 306 305 A1 304 303 A10 302 301 A11 300 299 A12 298 IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL AT91SAM9G20 JTAG Boundary Scan Register Pin Name Pin Type Associated BSR Cells CONTROL 62 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 12-2. 297 A13 296 295 A14 294 293 A15 292 291 A16 290 289 A17 288 287 A18 286 285 A19 284 283 A2 282 281 A20 280 279 A21 278 277 A22 276 275 A3 274 273 A4 272 271 A5 270 269 A6 268 267 A7 266 265 A8 264 263 A9 262 261 BMS INPUT IN/OUT INPUT/OUTPUT INPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL AT91SAM9G20 JTAG Boundary Scan Register CONTROL 63 6384D-ATARM-04-May-09 Table 12-2. 260 AT91SAM9G20 JTAG Boundary Scan Register CONTROL CAS IN/OUT INPUT/OUTPUT CONTROL D0 IN/OUT INPUT/OUTPUT CONTROL D1 IN/OUT INPUT/OUTPUT CONTROL D10 IN/OUT INPUT/OUTPUT CONTROL D11 IN/OUT INPUT/OUTPUT CONTROL D12 IN/OUT INPUT/OUTPUT CONTROL D13 IN/OUT INPUT/OUTPUT CONTROL D14 IN/OUT INPUT/OUTPUT CONTROL D15 IN/OUT INPUT/OUTPUT CONTROL D2 IN/OUT INPUT/OUTPUT CONTROL D3 IN/OUT INPUT/OUTPUT CONTROL D4 IN/OUT INPUT/OUTPUT CONTROL D5 IN/OUT INPUT/OUTPUT CONTROL D6 IN/OUT INPUT/OUTPUT CONTROL D7 IN/OUT INPUT/OUTPUT CONTROL D8 IN/OUT INPUT/OUTPUT CONTROL D9 IN/OUT INPUT/OUTPUT CONTROL NANDOE IN/OUT INPUT/OUTPUT 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 64 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 12-2. 224 NANDWE 223 222 NCS0 221 220 NCS1 219 218 NRD 217 216 NRST 215 214 NWR0 213 212 NWR1 211 210 NWR3 209 208 207 PA0 206 205 PA1 204 203 PA10 202 201 PA11 200 199 PA12 198 197 PA13 196 195 PA14 194 193 PA15 192 191 PA16 190 189 PA17 188 IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL OSCSEL INPUT IN/OUT INPUT/OUTPUT INPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL AT91SAM9G20 JTAG Boundary Scan Register CONTROL 65 6384D-ATARM-04-May-09 Table 12-2. 187 AT91SAM9G20 JTAG Boundary Scan Register CONTROL PA18 IN/OUT INPUT/OUTPUT CONTROL PA19 IN/OUT INPUT/OUTPUT CONTROL PA2 IN/OUT INPUT/OUTPUT CONTROL PA20 IN/OUT INPUT/OUTPUT CONTROL PA21 IN/OUT INPUT/OUTPUT CONTROL PA22 IN/OUT INPUT/OUTPUT CONTROL PA23 IN/OUT INPUT/OUTPUT CONTROL PA24 IN/OUT INPUT/OUTPUT CONTROL PA25 IN/OUT INPUT/OUTPUT CONTROL PA26 IN/OUT INPUT/OUTPUT CONTROL PA27 IN/OUT INPUT/OUTPUT CONTROL PA28 IN/OUT INPUT/OUTPUT CONTROL PA29 IN/OUT INPUT/OUTPUT CONTROL PA3 IN/OUT INPUT/OUTPUT internal internal internal internal CONTROL PA4 IN/OUT INPUT/OUTPUT CONTROL PA5 IN/OUT INPUT/OUTPUT 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 66 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 12-2. 151 PA6 150 149 PA7 148 147 PA8 146 145 PA9 144 143 PB0 142 141 PB1 140 139 PB10 138 137 PB11 136 135 134 133 132 131 PB14 130 129 PB15 128 127 PB16 126 125 PB17 124 123 PB18 122 121 PB19 120 119 PB2 118 117 PB20 116 IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL internal internal internal internal CONTROL IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL AT91SAM9G20 JTAG Boundary Scan Register CONTROL 67 6384D-ATARM-04-May-09 Table 12-2. 115 AT91SAM9G20 JTAG Boundary Scan Register CONTROL PB21 IN/OUT INPUT/OUTPUT CONTROL PB22 IN/OUT INPUT/OUTPUT CONTROL PB23 IN/OUT INPUT/OUTPUT CONTROL PB24 IN/OUT INPUT/OUTPUT CONTROL PB25 IN/OUT INPUT/OUTPUT CONTROL PB26 IN/OUT INPUT/OUTPUT CONTROL PB27 IN/OUT INPUT/OUTPUT CONTROL PB28 IN/OUT INPUT/OUTPUT CONTROL PB29 IN/OUT INPUT/OUTPUT CONTROL PB3 IN/OUT INPUT/OUTPUT CONTROL PB30 IN/OUT INPUT/OUTPUT CONTROL PB31 IN/OUT INPUT/OUTPUT CONTROL PB4 IN/OUT INPUT/OUTPUT CONTROL PB5 IN/OUT INPUT/OUTPUT CONTROL PB6 IN/OUT INPUT/OUTPUT CONTROL PB7 IN/OUT INPUT/OUTPUT CONTROL PB8 IN/OUT INPUT/OUTPUT CONTROL PB9 IN/OUT INPUT/OUTPUT 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 68 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 12-2. 79 PC0 78 77 PC1 76 75 PC10 74 73 PC11 72 71 70 69 PC13 68 67 PC14 66 65 PC15 64 63 PC16 62 61 PC17 60 59 PC18 58 57 PC19 56 55 54 53 PC20 52 51 PC21 50 49 PC22 48 47 PC23 46 45 PC24 44 IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL internal internal CONTROL IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL internal internal CONTROL IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL AT91SAM9G20 JTAG Boundary Scan Register CONTROL 69 6384D-ATARM-04-May-09 Table 12-2. 43 AT91SAM9G20 JTAG Boundary Scan Register CONTROL PC25 IN/OUT INPUT/OUTPUT CONTROL PC26 IN/OUT INPUT/OUTPUT CONTROL PC27 IN/OUT INPUT/OUTPUT CONTROL PC28 IN/OUT INPUT/OUTPUT CONTROL PC29 IN/OUT INPUT/OUTPUT internal internal CONTROL PC30 IN/OUT INPUT/OUTPUT CONTROL PC31 IN/OUT INPUT/OUTPUT CONTROL PC4 IN/OUT INPUT/OUTPUT CONTROL PC5 IN/OUT INPUT/OUTPUT CONTROL PC6 IN/OUT INPUT/OUTPUT CONTROL PC7 IN/OUT INPUT/OUTPUT CONTROL PC8 IN/OUT INPUT/OUTPUT CONTROL PC9 IN/OUT INPUT/OUTPUT CONTROL RAS IN/OUT INPUT/OUTPUT CONTROL RTCK OUT OUTPUT CONTROL SDA10 IN/OUT INPUT/OUTPUT CONTROL SDCK IN/OUT INPUT/OUTPUT 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 70 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 12-2. 07 SDCKE 06 05 SDWE 04 03 SHDN 02 01 00 TST WKUP INPUT INPUT OUT OUTPUT INPUT INPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL AT91SAM9G20 JTAG Boundary Scan Register CONTROL 71 6384D-ATARM-04-May-09 12.5.6 JID Code Register Access: Read-only 31 30 29 28 27 26 25 24 VERSION 23 22 21 20 19 PART NUMBER 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER 7 6 5 4 3 MANUFACTURER IDENTITY 2 1 0 MANUFACTURER IDENTITY 1 * VERSION[31:28]: Product Version Number Set to 0x0. * PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B24 * MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_403F. 72 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 13. AT91SAM9G20 Boot Program 13.1 Overview The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. The Boot program tries to detect SPI flash memories. The Serial Flash Boot program and DataFlash(R) Boot program are executed. It looks for a sequence of seven valid ARM exception vectors in a Serial Flash or DataFlash connected to the SPI. All these vectors must be B-branch or LDR load register instructions except for the sixth vector. This vector is used to store the size of the image to download. If a valid sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM vector sequence is found, NAND Flash Boot program is then executed. The NAND Flash Boot program looks for a sequence of seven valid ARM exception vectors. If such a sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM exception vector is found, the SDCard Boot program is then executed. It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SDCard. If such a file is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If the SDCard is not formatted or if boot.bin file is not found, TWI Boot program is then executed. The TWI Boot program searches for a valid application in an EEPROM memory. If such a file is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no validapplication is found, SAM-BA Boot is then executed. It waits for transactions either on the USB device, or on the DBGU serial port. 13.2 Flow Diagram The Boot Program implements the algorithm in Figure 13-1. 73 6384D-ATARM-04-May-09 Figure 13-1. Boot Program Algorithm Flow Diagram Device Setup SPI Serialflash Boot NPCS0 Yes Download from Serial flash NPCS0 Run Serial Flash Boot NPCS0 No Timeout < 25 ms SPI Dataflash Boot NPCS0 Yes Download from Dataflash NPCS0 DataFlash Boot NPCS0 Run No Timeout < 25 ms SPI Serialflash Boot NPCS1 Yes Download from Serial flash NPCS1 Run Serial Flash Boot NPCS1 No Timeout < 25 ms SPI Dataflash Boot NPCS1 Yes Download from Dataflash NPCS1 DataFlash Boot NPCS1 Run No Timeout < 25 ms NandFlash Boot Yes Download from NandFlash Run NandFlash Boot No Timeout < 50ms SD Card Boot Yes Download from SDCARD Run SD Card Boot No Timeout < 50ms EEPROMBoot Yes Download from EEPROM Run TWI/EEPROM Boot No Timeout 50ms. Character(s) received on DBGU OR USB Enumeration Successful Run SAM-BA Boot SAM-BA Boot Run SAM-BA Boot 74 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 13.3 Device Initialization Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode 2. Main Oscillator Frequency Detection 3. C variable initialization 4. PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB. - If internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is active, TTable 13-1 defines the crystals supported by the Boot Program when using the internal RC oscillator. als supported by the Boot Program. Table 13-1. Crystals Supported by Software Auto-Detection (MHz) 3.0 Boot in DBGU Boot on USB Note: Yes Yes 8.0 Yes Yes 18.432 Yes Yes Other Yes No Any other crystal can be used but it prevents using the USB. - If internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is bypassed, Table 13-2 defines the frequencies supported by the Boot Program when bypass-ing main oscillator. . Table 13-2. Crystals Supported by Software Auto-Detection (MHz) 3.0 Boot in DBGU Boot on USB Note: Yes Yes 8.0 Yes Yes 20 Yes Yes 50 Yes Yes Other Yes No Any other crystal can be used but it prevents using the USB. - If an external 32768 Hz Oscillator is used (OSCSEL = 1), defines the crystals supported by the Boot Program. Table 13-3 defines the crystals supported by the Boot Program. Table 13-3. 3.0 4.433619 6.0 7.3728 11.05920 14.7456 Note: Crystals Supported by Software Auto-Detection (MHz) 3.2768 4.608 6.144 7.864320 12.0 16.0 3.6864 4.9152 6.4 8.0 12.288 17.734470 3.84 5.0 6.5536 9.8304 13.56 18.432 4.0 5.24288 7.159090 10.0 14.31818 20.0 Booting either on USB or on DBGU is possible with any of these input frequencies. 75 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary - If an external 32768 Hz Oscillator is used (OSCSEL = 1) and Main Oscillator is bypassed. Table 13-4 defines the crystals supported by the Boot Program. Table 13-4. 3.0 4.433619 6.0 7.3728 11.05920 14.7456 24.0 33.0 Note: Input Frequencies Supported (OSCEL = 1) 3.2768 4.608 6.144 7.864320 12.0 16.0 24.576 40.0 3.6864 4.9152 6.4 8.0 12.288 17.734470 25.0 48.0 3.84 5.0 6.5536 9.8304 13.56 18.432 28.224 50 4.0 5.24288 7.159090 10.0 14.31818 20.0 32.0 Booting either on USB or on DBGU is possible with any of these input frequencies. 5. Initialization of the DBGU serial port (115200 bauds, 8, N, 1) 6. Jump to Serial Flash Boot sequence through NPCS0. If Serial Flash Boot succeeds, perform a remap and jump to 0x0. 7. Jump to DataFlash Boot sequence through NPCS0. If DataFlash Boot succeeds, perform a remap and jump to 0x0. 8. Jump to Serial Flash Boot sequence through NPCS1. If Serial Flash Boot succeeds, perform a remap and jump to 0x0. 9. Jump to DataFlash Boot sequence through NPCS1. If DataFlash Boot succeeds, perform a remap and jump to 0x0. 10. Jump to NAND Flash Boot sequence. If NAND Flash Boot succeeds, perform a remap and jump to 0x0. 11. Jump to SDCard Boot sequence. If SDCard Boot succeeds, perform a remap and jump to 0x0. 12. Jump to EEPROM Boot sequence. If EEPROM Boot succeeds, perform a remap and jump to 0x0. 13. Activation of the Instruction Cache 14. Jump to SAM-BA Boot sequence 15. Disable the WatchDog 16. Initialization of the USB Device Port 76 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 13-2. Remap Action after Download Completion 0x0000_0000 Internal ROM REMAP 0x0020_0000 Internal SRAM Internal ROM 0x0010_0000 Internal SRAM 0x0000_0000 13.4 Valid Image Detection The DataFlash Boot software looks for a valid application by analyzing the first 28 bytes corresponding to the ARM exception vectors. These bytes must implement ARM instructions for either branch or load PC with PC relative addressing. The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with his/her own vector (see "Structure of ARM Vector 6" on page 77). 13.4.1 Valid ARM exception vectors Figure 13-3. LDR Opcode 31 1 1 1 28 27 0 0 1 I 24 23 P U 0 W 20 19 1 Rn 16 15 Rd 12 11 0 Figure 13-4. B Opcode 31 1 1 1 28 27 0 1 0 1 24 23 0 Offset (24 bits) 0 Unconditional instruction: 0xE for bits 31 to 28 Load PC with PC relative addressing instruction: - Rn = Rd = PC = 0xF - I==0 - P==1 - U offset added (U==1) or subtracted (U==0) - W==1 13.4.2 Structure of ARM Vector 6 The ARM exception vector 6 is used to store information needed by the DataFlash boot program. This information is described below. 77 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 13-5. Structure of the ARM Vector 6 31 Size of the code to download in bytes 0 13.4.2.1 Example An example of valid vectors follows: 00 04 08 0c 10 14 18 ea000006 eafffffe ea00002f eafffffe eafffffe 00001234 eafffffe B B B B B B B 0x20 0x04 _main 0x0c 0x10 0x14 0x18 <- Code size = 4660 bytes The size of the image to load into SRAM is contained in the location of the sixth ARM vector. Thus the user must replace this vector by the correct size of his/her application. 13.5 Serial Flash Boot The Serial Flash boot looks for a valid application in the SPI Serial Flash memory. SPI0 is configured in master mode to generate a SPCK at 8 MHz. Serial Flash shall be connected to NPCS0 or NPCS1. The Serial Flash boot reads the Serial Flash status register (Instruction code 0x05). The Serial Flash is considered as ready if bit 0 of the returned status register is cleared. If no Serial Flash is connected or if it does not answer, Serial Flash boot exits after 1000 attempts. If the Serial Flash is ready, Serial Flash boot reads the first 8 words into SRAM (Instruction code "Continuos read array" 0x0b) and checks if it corresponds to valid exception vectors according to the Valid Image detection algorithm. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a second-level bootloader. 78 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 13-6. Serial Flash Download Start Send status command (0x05) Is status OK ? No Jump to next boot solution Yes Read the first 8 instructions (0x0b). Decode the sixth ARM vector 8 vectors (except vector 6) are LDR or Branch instruction No Yes Read the SerialFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the PC to 0 and perform the REMAP to jump to the downloaded application End 13.6 DataFlash Boot Sequence The DataFlash boot looks for a valid application in the SPI DataFlash memory. SPI0 is configured in master mode to generate a SPCK at 8 MHz. DataFlash shall be connected to NPCS0 or NPCS1. The DataFlash boot reads the DataFlash flash status register (Instruction code 0xD7). The DataFlash is considered as ready if bit 7 of the returned status register is set. If no DataFlash is connected or if it does not answer, DataFlash boot exits after 1000 attempts. If the DataFlash is ready, DataFlash boot reads the first 8 words into SRAM (Instruction code "Continuous Read Array" 0x0b) and checks if it corresponds to valid exception vectors according to the Valid Image detection algorithm. 79 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a second-level bootloader. The DataFlash boot is configured to be compatible with the future design of the DataFlash. Figure 13-7. Serial DataFlash Download Start Send status command Is status OK ? No Jump to next boot solution Yes Read the first 8 instructions (32 bytes). Decode the sixth ARM vector 8 vectors (except vector 6) are LDR or Branch instruction No Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the PC to 0 and perform the REMAP to jump to the downloaded application End 80 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 13.7 NAND Flash Boot The NAND Flash Boot program searches for a valid application in the NAND Flash memory. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. See "Valid Image Detection" on page 77 for more information on Valid Image Detection. 13.7.1 Supported NAND Flash Devices Any 8- or 16-bit NAND Flash Device. 13.8 SDCard Boot The SDCard Boot program searches for a valid application in the SD Card memory. (Boot ROM does not support high capacity SDCards.) It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SD Card. If a valid file is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a second-level bootloader. 13.9 EEPROM Boot The EEPROM Boot program searches for a valid application in an EEPROM connected to the TWI address: 0x0050_0000. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. See "Valid Image Detection" on page 77 for more information on Valid Image Detection. 81 6384D-ATARM-04-May-09 13.10 SAM-BA Boot If no valid DataFlash device has been found during the DataFlash boot sequence, the SAM-BA boot program is performed. The SAM-BA boot principle is to: - Wait for USB Device enumeration. - In parallel, wait for character(s) received on the DBGU. - Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as in Table 13-5. Table 13-5. Command O o H h W w S R G V Commands Available through the SAM-BA Boot Action write a byte read a byte write a half word read a half word write a word read a word send a file receive a file go display version Argument(s) Address, Value# Address,# Address, Value# Address,# Address, Value# Address,# Address,# Address, NbOfBytes# Address# No argument Example O200001,CA# o200001,# H200002,CAFE# h200002,# W200000,CAFEDECA# w200000,# S200000,# R200000,1234# G200200# V# * Write commands: Write a byte (O), a halfword (H) or a word (W) to the target. - Address: Address in hexadecimal. - Value: Byte, halfword or word to write in hexadecimal. - Output: `>'. * Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. - Address: Address in hexadecimal - Output: The byte, halfword or word read in hexadecimal following by `>' * Send a file (S): Send a file to a specified address - Address: Address in hexadecimal - Output: `>'. Note: There is a time-out on this command which is reached when the prompt `>' appears before the end of the command execution. * Receive a file (R): Receive data into a file from a specified address - Address: Address in hexadecimal - NbOfBytes: Number of bytes in hexadecimal to receive - Output: `>' * Go (G): Jump to a specified address and execute the code - Address: Address to jump in hexadecimal - Output: `>' * Get Version (V): Return the SAM-BA boot version - Output: `>' 82 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 13.10.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. 13.10.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Device 83 6384D-ATARM-04-May-09 13.10.3 USB Device Port A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device initialization procedure with PLLB configuration. The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows(R), from Windows 98SE to Windows XP(R). The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is Atmel's vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document "USB Basic Application", literature number 6123, for more details. 13.10.3.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 13-6. Request GET_DESCRIPTOR SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION GET_STATUS SET_FEATURE CLEAR_FEATURE Handled Standard Requests Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value. Returns status for the specified recipient. Used to set or enable a specific feature. Used to clear or disable a specific feature. The device also handles some class requests defined in the CDC class. Table 13-7. Request SET_LINE_CODING GET_LINE_CODING SET_CONTROL_LINE_STATE Handled Class Requests Definition Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 84 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 13.10.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAMBA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. 85 6384D-ATARM-04-May-09 13.11 Hardware and Software Constraints * The DataFlash, Serial Flash, NAND Flash, SDCard(1), and EEPROM downloaded code size must be inferior to 16K bytes. * The code is always downloaded from the device address 0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after remap). * The downloaded code must be position-independent or linked at address 0x0000_0000. * The DataFlash must be connected to NPCS0 of the SPI. Note: 1. Boot ROM does not support high capacity SDCards. The SPI and NAND Flash drivers use several PIOs in alternate functions to communicate with devices. Care must be taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and electrical conflicts between SPI output pins and the connected devices may appear. To assure correct functionality, it is recommended to plug in critical devices to other pins. Table 13-8 contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state. Table 13-8. Peripheral SPI0 SPI0 SPI0 SPI0 SPI0 PIOC Address Bus Address Bus MCI0 MCI0 MCI0 MCI0 MCI0 MCI0 TWI TWI DBGU DBGU Pins Driven during Boot Program Execution Pin MOSI MISO SPCK NPCS0 NPCS1 NANDCS NAND CLE NAND ALE MCDA0 MCCDA MCCK MCDA1 MCDA2 MCDA3 TWCK TWD DRXD DTXD PIO Line PIOA1 PIOA0 PIOA2 PIOA3 PIOC11 PIOC14 A22 A21 PIOA6 PIOA7 PIOA8 PIOA9 PIOA10 PIOA11 PIOA24 PIOA23 PIOB14 PIOB15 86 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 14. Reset Controller (RSTC) 14.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.2 Block Diagram Figure 14-1. Reset Controller Block Diagram Reset Controller Main Supply POR Backup Supply POR Startup Counter rstc_irq Reset State Manager proc_nreset user_reset NRST nrst_out NRST Manager exter_nreset periph_nreset backup_neset WDRPROC wd_fault SLCK 87 6384D-ATARM-04-May-09 14.3 14.3.1 Functional Description Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: * proc_nreset: Processor reset line. It also resets the Watchdog Timer. * backup_nreset: Affects all the peripherals powered by VDDBU. * periph_nreset: Affects the whole set of embedded peripherals. * nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical Characteristics section of the product documentation. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on. 14.3.2 NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 14-2 shows the block diagram of the NRST Manager. Figure 14-2. NRST Manager RSTC_MR RSTC_SR URSTIEN rstc_irq RSTC_MR URSTS NRSTL Other interrupt sources user_reset URSTEN NRST RSTC_MR ERSTL nrst_out External Reset Timer exter_nreset 14.3.2.1 NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. 88 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. 14.3.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the "nrst_out" signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 s and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator. 14.3.3 BMS Sampling The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. Figure 14-3. BMS Sampling SLCK Core Supply POR output XXX BMS sampling delay = 3 cycles BMS Signal H or L proc_nreset 14.3.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 14.3.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the 89 6384D-ATARM-04-May-09 device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 3 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0. When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 14-4 shows how the General Reset affects the reset signals. Figure 14-4. General Reset State SLCK MCK Backup Supply POR output Any Freq. Startup Time Main Supply POR output backup_nreset Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset XXX 0x0 = General Reset XXX NRST (nrst_out) BMS Sampling EXTERNAL RESET LENGTH = 2 cycles 90 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 14.3.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset. The "nrst_out" remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the Main Supply POR. Figure 14-5. Wake-up State SLCK MCK Main Supply POR output Any Freq. backup_nreset Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP XXX 0x1 = WakeUp Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) 14.3.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. 91 6384D-ATARM-04-May-09 When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 14-6. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Any XXX 0x4 = User Reset NRST (nrst_out) >= EXTERNAL RESET LENGTH 14.3.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: * PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. * PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. * EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. 92 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 14-7. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 cycle Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) Any XXX 0x3 = Software Reset SRCMP in RSTC_SR 14.3.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: * If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. * If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. 93 6384D-ATARM-04-May-09 When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 14-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 Any XXX 0x2 = Watchdog Reset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 14.3.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: * Backup Reset * Wake-up Reset * Watchdog Reset * Software Reset * User Reset Particular cases are listed below: * When in User Reset: - A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. - A software reset is impossible, since the processor reset is being activated. * When in Software Reset: - A watchdog event has priority over the current state. - The NRST has no effect. * When in Watchdog Reset: - The processor reset is active and so a Software Reset cannot be programmed. - A User Reset cannot be entered. 94 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 14.3.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: * RSTTYP field: This field gives the type of the last reset, as explained in previous sections. * SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. * NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. * URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 14-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 14-9. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization NRST NRSTL 2 cycle resynchronization URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 95 6384D-ATARM-04-May-09 14.4 Reset Controller (RSTC) User Interface Register Mapping Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read-write Reset Value 0x0000_0001 0x0000_0000 0x0000_0000 Back-up Reset Value Table 14-1. Offset 0x00 0x04 0x08 Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 96 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 14.4.1 Name: Reset Controller Control Register RSTC_CR Access Type:Write-only 31 30 29 28 KEY 23 - 15 - 7 - 22 - 14 - 6 - 21 - 13 - 5 - 20 - 12 - 4 - 19 - 11 - 3 EXTRST 18 - 10 - 2 PERRST 17 - 9 16 - 8 - 0 PROCRST 27 26 25 24 1 - * PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. * PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. * EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 97 6384D-ATARM-04-May-09 14.4.2 Name: Reset Controller Status Register RSTC_SR Access Type:Read-only 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 25 - 17 SRCMP 9 RSTTYP 1 - 24 - 16 NRSTL 8 2 - 0 URSTS * URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. * RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Reset Type General Reset Wake Up Reset Watchdog Reset Software Reset User Reset Comments Both VDDCORE and VDDBU rising VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low * NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). * SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 98 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 14.4.3 Name: Reset Controller Mode Register RSTC_MR Access Type:Read-write 31 30 29 28 KEY 23 - 15 - 7 - 22 - 14 - 6 - 21 - 13 - 5 20 - 12 - 4 URSTIEN 19 - 11 18 - 10 ERSTL 3 - 2 - 1 - 0 URSTEN 17 - 9 16 27 26 25 24 8 * URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. * URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. * ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 s and 2 seconds. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 99 6384D-ATARM-04-May-09 100 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 15. Real-time Timer (RTT) 15.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 15.2 Block Diagram Figure 15-1. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST 1 0 RTTINCIEN 0 RTT_SR set RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS set = RTT_AR ALMV rtt_alarm 15.3 Functional Description The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. 101 6384D-ATARM-04-May-09 The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. 2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register). Figure 15-2. RTT Counting APB cycle APB cycle MCK RTPRES - 1 Prescaler 0 RTT 0 ... ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface read RTT_SR 102 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 15.4 Real-time Timer (RTT) User Interface Register Mapping Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read-write Read-write Read-only Read-only Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 Table 15-1. Offset 0x00 0x04 0x08 0x0C 103 6384D-ATARM-04-May-09 15.4.1 Real-time Timer Mode Register Register Name: RTT_MR Access Type: Read/Write 31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RTPRES 7 6 5 4 RTPRES 3 2 1 0 27 - 19 - 11 26 - 18 RTTRST 10 25 - 17 RTTINCIEN 9 24 - 16 ALMIEN 8 * RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216. RTPRES ...0: The prescaler period is equal to RTPRES. * ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt. * RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt. * RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 104 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 15.4.2 Real-time Timer Alarm Register Register Name: RTT_AR Access Type: Read/Write 31 30 29 28 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 * ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 15.4.3 Real-time Timer Value Register Register Name: RTT_VR Access Type: Read-only 31 30 29 28 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 * CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 105 6384D-ATARM-04-May-09 15.4.4 Real-time Timer Status Register Register Name: RTT_SR Access Type: Read-only 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 RTTINC 24 - 16 - 8 - 0 ALMS * ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR. * RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR. 106 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 16. Periodic Interval Timer (PIT) 16.1 Overview The Periodic Interval Timer (PIT) provides the operating system's scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.2 Block Diagram Figure 16-1. Periodic Interval Timer PIT_MR PIV =? PIT_MR PITIEN set 0 PIT_SR PITS reset pit_irq 0 0 1 0 1 12-bit Adder read PIT_PIVR MCK 20-bit Counter Prescaler MCK/16 CPIV PIT_PIVR PICNT CPIV PIT_PIIR PICNT 16.3 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). 107 6384D-ATARM-04-May-09 Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 16-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 16-2. Enabling/Disabling PIT with PITEN APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN APB cycle CPIV PICNT PITS (PIT_SR) APB Interface 0 1 0 PIV - 1 PIV 1 0 0 1 read PIT_PIVR 108 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 16.4 Periodic Interval Timer (PIT) User Interface Register Mapping Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read-write Read-only Read-only Read-only Reset 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 Table 16-1. Offset 0x00 0x04 0x08 0x0C 109 6384D-ATARM-04-May-09 16.4.1 Name: Access: 31 - 23 - 15 Periodic Interval Timer Mode Register PIT_MR Read/Write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 PIV 7 6 5 4 PIV 3 2 1 0 27 - 19 26 - 18 PIV 11 10 9 8 25 PITIEN 17 24 PITEN 16 * PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). * PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. * PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. 110 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 16.4.2 Name: Access: 31 - 23 - 15 - 7 - Periodic Interval Timer Status Register PIT_SR Read-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 PITS * PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 16.4.3 Name: Access: 31 Periodic Interval Timer Value Register PIT_PIVR Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 Reading this register clears PITS in PIT_SR. * CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. * PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 111 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 16.4.4 Name: Access: 31 Periodic Interval Timer Image Register PIT_PIIR Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 * CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. * PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 112 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 17. Watchdog Timer (WDT) 17.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 17.2 Block Diagram Figure 17-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDT_CR WDRSTT reload 1 0 WDV 12-bit Down Counter WDT_MR WDD Current Value reload 1/128 SLCK <= WDD WDT_MR WDRSTEN =0 wdt_fault (to Reset Controller) wdt_int set set read WDT_SR or reset WDERR reset WDUNF reset WDFIEN WDT_MR 113 6384D-ATARM-04-May-09 17.3 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz). After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires. The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters. In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the "wdt_fault" signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR). To prevent a software deadlock that continuously triggers the Watchdog, the reload of the Watchdog must occur while the Watchdog counter is within a window between 0 and WDD, WDD is defined in the WatchDog Mode Register WDT_MR. Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the "wdt_fault" signal to the Reset Controller is asserted. Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the WDD and WDV values are equal). The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit WDFIEN is set in the mode register. The signal "wdt_fault" to the reset controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset. If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the "wdt_fault" signal to the reset controller is deasserted. Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. 114 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 17-2. Watchdog Behavior Watchdog Error Watchdog Underflow if WDRSTEN is 1 FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 WDT_CR = WDRSTT if WDRSTEN is 0 Watchdog Fault 115 6384D-ATARM-04-May-09 17.4 Watchdog Timer (WDT) User Interface Register Mapping Register Control Register Mode Register Status Register Name WDT_CR WDT_MR WDT_SR Access Write-only Read-write Once Read-only Reset 0x3FFF_2FFF 0x0000_0000 Table 17-1. Offset 0x00 0x04 0x08 17.4.1 Watchdog Timer Control Register Register Name:WDT_CR Access Type: Write-only 31 30 29 28 KEY 23 - 15 - 7 - 22 - 14 - 6 - 21 - 13 - 5 - 20 - 12 - 4 - 19 - 11 - 3 - 18 - 10 - 2 - 17 - 9 - 1 - 16 - 8 - 0 WDRSTT 27 26 25 24 * WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 116 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 17.4.2 Watchdog Timer Mode Register Register Name: WDT_MR Access Type: 31 Read-write Once 30 29 WDIDLEHLT 21 28 WDDBGHLT 20 WDD 27 26 WDD 19 18 17 16 25 24 23 22 15 WDDIS 7 14 WDRPROC 6 13 WDRSTEN 5 12 WDFIEN 4 WDV 11 10 WDV 9 8 3 2 1 0 * WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. * WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt. 1: A Watchdog fault (underflow or error) asserts interrupt. * WDRSTEN: Watchdog Reset Enable 0: A Watchdog fault (underflow or error) has no effect on the resets. 1: A Watchdog fault (underflow or error) triggers a Watchdog reset. * WDRPROC: Watchdog Reset Processor 0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets. 1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset. * WDD: Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer. If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer. If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error. * WDDBGHLT: Watchdog Debug Halt 0: The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state. * WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. * WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 117 6384D-ATARM-04-May-09 17.4.3 Watchdog Timer Status Register Register Name: WDT_SR Access Type: Read-only 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 WDERR 24 - 16 - 8 - 0 WDUNF * WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR. * WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR. 1: At least one Watchdog error occurred since the last read of WDT_SR. 118 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 18. Shutdown Controller (SHDWC) 18.1 Overview The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 18.2 Block Diagram Figure 18-1. Shutdown Controller Block Diagram SLCK Shutdown Controller SHDW_MR read SHDW_SR reset CPTWK0 WKMODE0 WKUP0 WAKEUP0 set SHDW_SR read SHDW_SR Wake-up reset RTTWKEN RTT Alarm SHDW_MR RTTWK set SHDW_SR SHDW_CR Shutdown Output Controller Shutdown SHDN SHDW 18.3 I/O Lines Description I/O Lines Description Description Wake-up 0 input Shutdown output Type Input Output Table 18-1. Name WKUP0 SHDN 18.4 18.4.1 Product Dependencies Power Management The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Controller has no effect on the behavior of the Shutdown Controller. 119 6384D-ATARM-04-May-09 18.5 Functional Description The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins and one output pin, SHDN. A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies of the system, and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to any push-buttons or signal that wake up the system. The software is able to control the pin SHDN by writing the Shutdown Control Register (SHDW_CR) with the bit SHDW at 1. The shutdown is taken into account only 2 slow clock cycles after the write of SHDW_CR. This register is password-protected and so the value written should contain the correct key for the command to be taken into account. As a result, the system should be powered down. A level change on WKUP0 is used as wake-up. Wake-up is configured in the Shutdown Mode Register (SHDW_MR). The transition detector can be programmed to detect either a positive or negative transition or any level change on WKUP0. The detection can also be disabled. Programming is performed by defining WKMODE0. Moreover, a debouncing circuit can be programmed for WKUP0. The debouncing circuit filters pulses on WKUP0 shorter than the programmed number of 16 SLCK cycles in CPTWK0 of the SHDW_MR register. If the programmed level change is detected on a pin, a counter starts. When the counter reaches the value programmed in the corresponding field, CPTWK0, the SHDN pin is released. If a new input change is detected before the counter reaches the corresponding value, the counter is stopped and cleared. WAKEUP0 of the Status Register (SHDW_SR) reports the detection of the programmed events on WKUP0 with a reset after the read of SHDW_SR. The Shutdown Controller can be programmed so as to activate the wake-up using the RTT alarm (the detection of the rising edge of the RTT alarm is synchronized with SLCK). This is done by writing the SHDW_MR register using the RTTWKEN fields. When enabled, the detection of the RTT alarm is reported in the RTTWK bit of the SHDW_SR Status register. It is reset after the read of SHDW_SR. When using the RTT alarm to wake up the system, the user must ensure that the RTT alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flag may be detected and the wake-up fails. 120 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 18.6 Shutdown Controller (SHDWC) User Interface Register Mapping Register Shutdown Control Register Shutdown Mode Register Shutdown Status Register Name SHDW_CR SHDW_MR SHDW_SR Access Write-only Read-write Read-only Reset 0x0000_0003 0x0000_0000 Table 18-2. Offset 0x00 0x04 0x08 121 6384D-ATARM-04-May-09 18.6.1 Shutdown Control Register Register Name: SHDW_CR Access Type: Write-only 31 30 29 28 KEY 23 - 15 - 7 - 22 - 14 - 6 - 21 - 13 - 5 - 20 - 12 - 4 - 19 - 11 - 3 - 18 - 10 - 2 - 17 - 9 - 1 - 16 - 8 - 0 SHDW 27 26 25 24 * SHDW: Shutdown Command 0 = No effect. 1 = If KEY is correct, asserts the SHDN pin. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 122 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 18.6.2 Shutdown Mode Register Register Name: SHDW_MR Access Type: Read/Write 31 - 23 - 15 30 - 22 - 14 CPTWK1 7 6 CPTWK0 5 4 29 - 21 - 13 28 - 20 - 12 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 WKMODE0 0 24 - 16 RTTWKEN 8 * WKMODE0: Wake-up Mode 0 WKMODE[1:0] 0 0 1 1 0 1 0 1 Wake-up Input Transition Selection None. No detection is performed on the wake-up input Low to high level High to low level Both levels change * CPTWK0: Counter on Wake-up 0 Defines the number of 16 Slow Clock cycles, the level detection on the corresponding input pin shall last before the wakeup event occurs. Because of the internal synchronization of WKUP0, the SHDN pin is released (CPTWK x 16 + 1) Slow Clock cycles after the event on WKUP. * RTTWKEN: Real-time Timer Wake-up Enable 0 = The RTT Alarm signal has no effect on the Shutdown Controller. 1 = The RTT Alarm signal forces the de-assertion of the SHDN pin. 123 6384D-ATARM-04-May-09 18.6.3 Shutdown Status Register Register Name: SHDW_SR Access Type: Read-only 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 WAKEUP0 * WAKEUP0: Wake-up 0 Status 0 = No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. 1 = At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. * RTTWK: Real-time Timer Wake-up 0 = No wake-up alarm from the RTT occurred since the last read of SHDW_SR. 1 = At least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. 124 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 19. AT91SAM9G20 Bus Matrix 19.1 Overview The Bus Matrix implements a multi-layer AHB based on the AHB-Lite protocol that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects 6 AHB Masters to 5 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix user interface is compliant with the ARM Advanced High-performance Bus and provides a Chip Configuration User Interface with registers that allow the Bus Matrix to support application specific features. 19.2 Memory Mapping The Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each AHB Master several memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e., external RAM, internal ROM or internal Flash, etc.) becomes possible. The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that performs remap action for every master independently. 19.3 Special Bus Granting Techniques The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This mechanism reduces latency at first accesses of a burst or single transfer. The bus granting mechanism sets a default master for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master and fixed default master. 19.3.1 No Default Master At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default Master suits Low Power mode. Last Access Master At the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. Fixed Default Master At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike last access master, the fixed master doesn't change unless the user modifies it by a software action (field FIXED_DEFMSTR of the related MATRIX_SCFG). To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register contains two fields, DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field is used to select the default master type (no default, last access master, fixed default master) whereas the 4-bit FIXED_DEFMSTR field is used to select a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Refer to Section 19.5 "Bus Matrix (MATRIX) User Interface" on page 128. 125 19.3.2 19.3.3 6384D-ATARM-04-May-09 19.4 Arbitration The Bus Matrix provides an arbitration mechanism that reduces latency when conflicting cases occur, in particular when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus arbitrating each slave differently. The Bus Matrix provides the user the possibility to choose between 2 arbitration types for each slave: 1. Round-Robin Arbitration (the default) 2. Fixed Priority Arbitration This choice is made through the field ARBT of the Slave Configuration Registers (MATRIX_SCFG). Each algorithm may be complemented by selecting a default master configuration for each slave. When a re-arbitration has to be done, it is realized only under specific conditions described in Section 19.4.1 "Arbitration Rules" on page 126. 19.4.1 Arbitration Rules Each arbiter has the ability to arbitrate between two or more different master's requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles: 1. Idle Cycles: when a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. Single Cycles: when a slave is currently doing a single access. 3. End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst (see Section 19.4.1.1 "Undefined Length Burst Arbitration" on page 126). 4. Slot Cycle Limit: when the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken (see Section 19.4.1.2 "Slot Cycle Limit Arbitration" on page 127). 19.4.1.1 Undefined Length Burst Arbitration In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as for defined length burst transfer, which is selected between the following: 1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer is never broken. 2. Four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside INCR transfer. 3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside INCR transfer. 4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer. This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG). 126 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 19.4.1.2 Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a very slow slave (e.g., an external low speed memory). At the beginning of the burst access, a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word transfer. Round-Robin Arbitration This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. If two or more master's requests arise at the same time, the master with the lowest number is first serviced then the others are serviced in a roundrobin manner. There are three round-robin algorithms implemented: * Round-Robin arbitration without default master * Round-Robin arbitration with last access master * Round-Robin arbitration with fixed default master 19.4.2.1 Round-Robin Arbitration without Default Master This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. At the end of the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters that perform significant bursts. Round-Robin Arbitration with Last Access Master This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. At the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performs the access. Other non privileged masters still get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform single accesses. Round-Robin Arbitration with Fixed Default Master This is another biased round-robin algorithm, it allows the Bus Matrix arbiters to remove the one latency cycle for the fixed default master per slave. At the end of the current access, the slave remains connected to its fixed default master. Requests attempted by this fixed default master do not cause any latency whereas other non privileged masters get one latency cycle. This technique can be used for masters that mainly perform single accesses. Fixed Priority Arbitration This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If two or more master's requests are active at the same time, the master with the highest priority number is serviced first. If two or more master's requests with the same priority are active at the same time, the master with the highest number is serviced first. For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS and MATRIX_PRBS). 127 6384D-ATARM-04-May-09 19.4.2 19.4.2.2 19.4.2.3 19.4.3 19.5 Bus Matrix (MATRIX) User Interface Register Mapping Register Master Configuration Register 0 Master Configuration Register 1 Master Configuration Register 2 Master Configuration Register 3 Master Configuration Register 4 Master Configuration Register 5 Reserved Slave Configuration Register 0 Slave Configuration Register 1 Slave Configuration Register 2 Slave Configuration Register 3 Slave Configuration Register 4 Reserved Priority Register A for Slave 0 Reserved Priority Register A for Slave 1 Reserved Priority Register A for Slave 2 Reserved Priority Register A for Slave 3 Reserved Priority Register A for Slave 4 Reserved Master Remap Control Register Reserved Name MATRIX_MCFG0 MATRIX_MCFG1 MATRIX_MCFG2 MATRIX_MCFG3 MATRIX_MCFG4 MATRIX_MCFG5 - MATRIX_SCFG0 MATRIX_SCFG1 MATRIX_SCFG2 MATRIX_SCFG3 MATRIX_SCFG4 - MATRIX_PRAS0 - MATRIX_PRAS1 - MATRIX_PRAS2 - MATRIX_PRAS3 - MATRIX_PRAS4 - MATRIX_MRCR - Access Read-write Read-write Read-write Read-write Read-write Write-only - Read-write Read-write Read-write Read-write Read-write - Read-write - Read-write - Read-write - Read-write - Read-write - Read-write - Reset 0x00000000 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 - 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - 0x00000000 - Table 19-1. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 - 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 - 0x007C 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A8 - 0x00FC 0x0100 0x0104 - 0x010C 128 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 19.5.1 Bus Matrix Master Configuration Registers Register Name:MATRIX_MCFG0...MATRIX_MCFG5 Access Type:Read-write (MATRIX_MCFG5 is Write-only) 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 25 - 17 - 9 - 1 ULBT 24 - 16 - 8 - 0 * ULBT: Undefined Length Burst Type 0: Infinite Length Burst No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. 1: Single Access The undefined length burst is treated as a succession of single accesses allowing rearbitration at each beat of the INCR burst. 2: Four Beat Burst The undefined length burst is split into 4-beat bursts allowing rearbitration at each 4-beat burst end. 3: Eight Beat Burst The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end. 4: Sixteen Beat Burst The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end. 129 6384D-ATARM-04-May-09 19.5.2 Bus Matrix Slave Configuration Registers Register Name:MATRIX_SCFG0...MATRIX_SCFG4 Access Type:Read-write 31 - 23 - 15 - 7 14 - 6 13 - 5 12 - 4 SLOT_CYCLE 30 - 22 29 - 21 28 - 20 27 - 19 FIXED_DEFMSTR 11 - 3 10 - 2 26 - 18 17 25 ARBT 16 24 DEFMSTR_TYPE 9 - 1 8 - 0 * SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave. This limit has been placed to avoid locking very slow slaves when very long bursts are used. This limit should not be very small though. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE. * DEFMSTR_TYPE: Default Master Type 0: No Default Master At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters. This results in one cycle latency for the first access of a burst transfer or for a single access. 1: Last Default Master At the end of current slave access, if no other master request is pending, the slave stays connected with the last master having accessed it. This results in not having the one cycle latency when the last master tries to access the slave again. 2: Fixed Default Master At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master whose number has been written in the FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master tries to access the slave again. * FIXED_DEFMSTR: Fixed Default Master This is the number of the Default Master for this slave. Only used if DEFMASTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMASTR_TYPE to 0. * ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority Arbitration 2: Reserved 3: Reserved 130 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 19.5.3 Bus Matrix Priority Registers For Slaves Register Name:MATRIX_PRAS0...MATRIX_PRAS4 Access Type:Read-write 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 5 M1PR 13 M3PR 4 29 - 21 M5PR 12 28 - 20 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 1 M0PR 9 M2PR 0 25 - 17 M4PR 8 24 - 16 * MxPR: Master x Priority Fixed priority of Master x for access to the selected slave. The higher the number, the higher the priority. 131 6384D-ATARM-04-May-09 19.5.4 Bus Matrix Master Remap Control Register Register Name:MATRIX_MRCR Access Type:Read-write Reset: 31 - 23 - 15 - 7 - 0x0000_0000 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 RCB1 24 - 16 - 8 - 0 RCB0 * RCBx: Remap Command Bit for AHB Master x 0: Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master 132 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 19.6 Chip Configuration User Interface Register Mapping Register Reserved EBI Chip Select Assignment Register Reserved Name - EBI_CSA - Access - Read-write - Reset - 0x00010000 - Table 19-2. Offset 0x0110 - 0x0118 0x011C 0x0130 - 0x01FC 19.6.1 EBI Chip Select Assignment Register Register Name:EBI_CSA Access Type:Read-write Reset: 31 - 23 - 15 - 7 - 0x0001_0000 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 EBI_CS5A 28 - 20 - 12 - 4 EBI_CS4A 27 - 19 - 11 - 3 EBI_CS3A 26 - 18 - 10 - 2 - 25 - 17 IOSR 9 - 1 EBI_CS1A 24 - 16 VDDIOMSEL 8 EBI_DBPUC 0 - * EBI_CS1A: EBI Chip Select 1 Assignment 0 = EBI Chip Select 1 is assigned to the Static Memory Controller. 1 = EBI Chip Select 1 is assigned to the SDRAM Controller. * EBI_CS3A: EBI Chip Select 3 Assignment 0 = EBI Chip Select 3 is only assigned to the Static Memory Controller and EBI_NCS3 behaves as defined by the SMC. 1 = EBI Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. * EBI_CS4A: EBI Chip Select 4 Assignment 0 = EBI Chip Select 4 is only assigned to the Static Memory Controller and EBI_NCS4 behaves as defined by the SMC. 1 = EBI Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. * EBI_CS5A: EBI Chip Select 5 Assignment 0 = EBI Chip Select 5 is only assigned to the Static Memory Controller and EBI_NCS5 behaves as defined by the SMC. 1 = EBI Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. * EBI_DBPUC: EBI Data Bus Pull-Up Configuration 0 = EBI D0 - D15 Data Bus bits are internally pulled-up to the VDDIOM power supply. 1 = EBI D0 - D15 Data Bus bits are not internally pulled-up. 133 6384D-ATARM-04-May-09 * VDDIOMSEL: Memory voltage selection 0 = Memories are 1.8V powered. 1 = Memories are 3.3V powered. * IOSR: I/O Slew Rate Selection Refer to the" I/Os" sub-section of the "Clock Characteristics" in the product "Electrical Characteristics". 134 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 20. AT91SAM9G20 External Bus Interface 20.1 Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and SDRAM. The EBI also supports the CompactFlash and the NAND Flash protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the EBI handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to eight chip select lines (NCS[7:0]) and several control pins that are generally multiplexed between the different external Memory Controllers. 135 6384D-ATARM-04-May-09 20.2 20.2.1 Block Diagram External Bus Interface Figure 20-1 shows the organization of the External Bus Interface. Figure 20-1. Organization of the External Bus Interface Bus Matrix External Bus Interface D[15:0] A0/NBS0 AHB SDRAM Controller A1/NWR2/NBS2 A[15:2], A[20:18] A16/BA0 A17/BA1 MUX Logic Static Memory Controller NCS0 NCS1/SDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE CompactFlash Logic RAS CAS SDWE SDA10 NAND Flash Logic A21/NANDALE A22/NANDCLE NANDOE NANDWE ECC Controller PIO Address Decoders Chip Select Assignor NCS3/NANDCS D[31:16] A[24:23] A25/CFRNW NCS4/CFCS0 NCS5/CFCS1 NCS2, NCS6, NCS7 User Interface NWAIT CFCE1 CFCE2 APB 136 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 20.3 I/O Lines Description EBI I/O Lines Description Function EBI EBI_D0 - EBI_D31 EBI_A0 - EBI_A25 EBI_NWAIT Data Bus Address Bus External Wait Signal SMC EBI_NCS0 - EBI_NCS7 EBI_NWR0 - EBI_NWR3 EBI_NRD EBI_NWE EBI_NBS0 - EBI_NBS3 Chip Select Lines Write Signals Read Signal Write Enable Byte Mask Signals EBI for CompactFlash Support EBI_CFCE1 - EBI_CFCE2 EBI_CFOE EBI_CFWE EBI_CFIOR EBI_CFIOW EBI_CFRNW EBI_CFCS0 - EBI_CFCS1 CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash I/O Read Signal CompactFlash I/O Write Signal CompactFlash Read Not Write Signal CompactFlash Chip Select Lines EBI for NAND Flash Support EBI_NANDCS EBI_NANDOE EBI_NANDWE NAND Flash Chip Select Line NAND Flash Output Enable NAND Flash Write Enable SDRAM Controller EBI_SDCK EBI_SDCKE EBI_SDCS EBI_BA0 - EBI_BA1 EBI_SDWE EBI_RAS - EBI_CAS EBI_NWR0 - EBI_NWR3 EBI_NBS0 - EBI_NBS3 EBI_SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Line Bank Select SDRAM Write Enable Row and Column Signal Write Signals Byte Mask Signals SDRAM Address 10 Line Output Output Output Output Output Output Output Output Output Low Low Low Low High Low Output Output Output Low Low Low Output Output Output Output Output Output Output Low Low Low Low Low Low Output Output Output Output Output Low Low Low Low Low I/O Output Input Low Type Active Level Table 20-1. Name 137 6384D-ATARM-04-May-09 The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment. Table 20-2 on page 138 details the connections between the two Memory Controllers and the EBI pins. Table 20-2. EBI Pins and Memory Controllers I/O Lines Connections EBIx Pins EBI_NWR1/NBS1/CFIOR EBI_A0/NBS0 EBI_A1/NBS2/NWR2 EBI_A[11:2] EBI_SDA10 EBI_A12 EBI_A[14:13] EBI_A[22:15] EBI_A[25:23] EBI_D[31:0] SDRAMC I/O Lines NBS1 Not Supported Not Supported SDRAMC_A[9:0] SDRAMC_A10 Not Supported SDRAMC_A[12:11] Not Supported Not Supported D[31:0] SMC I/O Lines NWR1/NUB SMC_A0/NLB SMC_A1 SMC_A[11:2] Not Supported SMC_A12 SMC_A[14:13] SMC_A[22:15] SMC_A[25:23] D[31:0] 138 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 20.4 20.4.1 Application Example Hardware Interface Table 20-3 on page 139 details the connections to be applied between the EBI pins and the external devices for each Memory Controller. EBI Pins and External Static Devices Connections Pins of the Interfaced Device Table 20-3. Signals: EBI_ Controller D0 - D7 D8 - D15 D16 - D23 D24 - D31 A0/NBS0 A1/NWR2/NBS2 A2 - A22 A23 - A25 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NCS4/CFCS0 NCS5/CFCS1 NCS6 NCS7 NRD/CFOE NWR0/NWE NWR1/NBS1 NWR3/NBS3 8-bit Static Device 2 x 8-bit Static Devices 16-bit Static Device SMC 4 x 8-bit Static Devices 2 x 16-bit Static Devices 32-bit Static Device D0 - D7 - - - A0 A1 A[2:22] A[23:25] CS CS CS CS CS CS CS CS OE WE - - D0 - D7 D8 - D15 - - - A0 A[1:21] A[22:24] CS CS CS CS CS CS CS CS OE WE WE - (1) (1) D0 - D7 D8 - D15 - - NLB A0 A[1:21] A[22:24] CS CS CS CS CS CS CS CS OE WE NUB - D0 - D7 D8 - D15 D16 - D23 D24 - D31 - WE(2) A[0:20] A[21:23] CS CS CS CS CS CS CS CS OE WE WE (2) (2) D0 - D7 D8 - 15 D16 - D23 D24 - D31 NLB (3) D0 - D7 D8 - 15 D16 - D23 D24 - D31 BE0(5) BE2(5) A[0:20] A[21:23] CS CS CS CS CS CS CS CS OE WE BE1(5) BE3(5) NLB(4) A[0:20] A[21:23] CS CS CS CS CS CS CS CS OE WE NUB (3) WE(2) NUB(4) Notes: 1. NWR1 enables upper byte writes. NWR0 enables lower byte writes. 2. NWRx enables corresponding byte x writes (x = 0,1,2 or 3). 3. NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word. 4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word. 5. BEx: Byte x Enable (x = 0,1,2 or 3). 139 6384D-ATARM-04-May-09 Table 20-4. EBI Pins and External Device Connections Pins of the Interfaced Device Signals: EBI_ Controller D0 - D7 D8 - D15 D16 - D31 A0/NBS0 A1/NWR2/NBS2 A2 - A10 A11 SDA10 A12 A13 - A14 A15 A16/BA0 A17/BA1 A18 - A20 A21/NANDALE A22/NANDCLE A23 - A24 A25 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NCS4/CFCS0 NCS5/CFCS1 NCS6 NCS7 NANDOE NANDWE NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW CFCE1 SDRAM SDRAMC D0 - D7 D8 - D15 D16 - D31 DQM0 DQM2 A[0:8] A9 A10 - A[11:12] - BA0 BA1 - - - - - - CS - - - - - - - - - - DQM1 DQM3 - CompactFlash (EBI only) CompactFlash True IDE Mode (EBI only) SMC NAND Flash D0 - D7 D8 - 15 - A0 A1 A[2:10] - - - - - - - - - REG - CFRNW - - - - CFCS0(1) CFCS1 - - - - OE WE IOR IOW CE1 (1) (1) D0 - D7 D8 - 15 - A0 A1 A[2:10] - - - - - - - - - REG - CFRNW - - - - CFCS0(1) CFCS1 - - - - - WE IOR IOW CS0 (1) (1) I/O0 - I/O7 I/O8 - I/O15 - - - - - - - - - - - - ALE CLE - - - - - CE(3) - - - - RE WE - - - - - 140 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 20-4. EBI Pins and External Device Connections (Continued) Pins of the Interfaced Device Signals: EBI_ Controller CFCE2 SDCK SDCKE RAS CAS SDWE NWAIT Pxx Pxx (2) (2) SDRAM SDRAMC - CLK CKE RAS CAS WE - - - - CompactFlash (EBI only) CompactFlash True IDE Mode (EBI only) SMC NAND Flash CE2 - - - - - WAIT CD1 or CD2 - - CS1 - - - - - WAIT CD1 or CD2 - - - - - - - - - - CE(3) RDY Pxx(2) Notes: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot. 2. Any PIO line. 3. CE connection depends on the NAND Flash. For standard NAND Flash devices, it must be connected to any free PIO line. For "CE don't care" NAND Flash devices, it can be either connected to NCS3/NANDCS or to any free PIO line. 141 6384D-ATARM-04-May-09 20.4.2 Connection Examples Figure 20-2 shows an example of connections between the EBI and external devices. Figure 20-2. EBI Connections to Memory Devices EBI D0-D31 RAS CAS SDCK SDCKE SDWE A0/NBS0 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NRD/NOE NWR0/NWE D0-D7 2M x 8 SDRAM D0-D7 D8-D15 2M x 8 SDRAM D0-D7 CS CLK CKE SDWE WE RAS CAS DQM NBS0 A0-A9, A11 A10 BA0 BA1 A2-A11, A13 SDA10 A16/BA0 A17/BA1 CS CLK CKE SDWE WE RAS CAS DQM NBS1 A0-A9, A11 A10 BA0 BA1 A2-A11, A13 SDA10 A16/BA0 A17/BA1 SDA10 A2-A15 A16/BA0 A17/BA1 A18-A25 D16-D23 D0-D7 NCS0 NCS1/SDCS NCS2 NCS3 NCS4 NCS5 CS CLK CKE SDWE WE RAS CAS DQM NBS2 2M x 8 SDRAM D24-D31 2M x 8 SDRAM D0-D7 A0-A9, A11 A10 BA0 BA1 A2-A11, A13 SDA10 A16/BA0 A17/BA1 CS CLK CKE SDWE WE RAS CAS DQM NBS3 A0-A9, A11 A10 BA0 BA1 A2-A11, A13 SDA10 A16/BA0 A17/BA1 128K x 8 SRAM D0-D7 D0-D7 A0-A16 A1-A17 D8-D15 128K x 8 SRAM D0-D7 A0-A16 A1-A17 CS OE NRD/NOE WE A0/NWR0/NBS0 CS OE NRD/NOE WE NWR1/NBS1 20.5 20.5.1 Product Dependencies I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller. 20.6 Functional Description The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements: * the Static Memory Controller (SMC) * the SDRAM Controller (SDRAMC) 142 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * the ECC Controller (ECC) * a chip select assignment feature that assigns an AHB address space to the external devices * a multiplex controller circuit that shares the pins between the different Memory Controllers * programmable CompactFlash support logic * programmable NAND Flash support logic 20.6.1 Bus Multiplexing The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the Memory Controllers. Furthermore, refresh cycles of the SDRAM are executed independently by the SDRAM Controller without delaying the other external Memory Controller accesses. 20.6.2 Pull-up Control The EBI_CSA Registers in the Chip Configuration User Interface permit enabling of on-chip pullup resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up resistors are enabled after reset. Setting the EBI_DBPUC bit disables the pull-up resistors on the D0 to D15 lines. Enabling the pull-up resistor on the D16-D31 lines can be performed by programming the appropriate PIO controller. Static Memory Controller For information on the Static Memory Controller, refer to the section "Static Memory Controller". SDRAM Controller For information on the SDRAM Controller, refer to the section "SDRAM Controller". ECC Controller For information on the ECC Controller, refer to the section "ECC Controller". CompactFlash Support The External Bus Interface integrates circuitry that interfaces to CompactFlash devices. The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or NCS5 address space. Programming the EBI_CS4A and/or EBI_CS5A bit of the EBI_CSA Register in the Chip Configuration User Interface to the appropriate value enables this logic. For details on this register, refer to the in the Bus Matrix Section. Access to an external CompactFlash device is then made by accessing the address space reserved to NCS4 and/or NCS5 (i.e., between 0x5000 0000 and 0x5FFF FFFF for NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. 20.6.3 20.6.4 20.6.5 20.6.6 143 6384D-ATARM-04-May-09 20.6.6.1 I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode Within the NCS4 and/or NCS5 address space, the current transfer address is used to distinguish I/O mode, common memory mode, attribute memory mode and True IDE mode. The different modes are accessed through a specific memory mapping as illustrated on Figure 20-3. A[23:21] bits of the transfer address are used to select the desired mode as described in Table 20-5 on page 144. Figure 20-3. CompactFlash Memory Mapping True IDE Alternate Mode Space Offset 0x00E0 0000 True IDE Mode Space Offset 0x00C0 0000 CF Address Space Offset 0x0080 0000 Common Memory Mode Space Offset 0x0040 0000 Attribute Memory Mode Space Offset 0x0000 0000 I/O Mode Space Note: The A22 pin is used to drive the REG signal of the CompactFlash Device (except in True IDE mode). Table 20-5. A[23:21] 000 010 100 110 111 CompactFlash Mode Selection Mode Base Address Attribute Memory Common Memory I/O Mode True IDE Mode Alternate True IDE Mode 20.6.6.2 CFCE1 and CFCE2 Signals To cover all types of access, the SMC must be alternatively set to drive 8-bit data bus or 16-bit data bus. The odd byte access on the D[7:0] bus is only possible when the SMC is configured to drive 8-bit memory devices on the corresponding NCS pin (NCS4 or NCS5). The Chip Select Register (DBW field in the corresponding Chip Select Register) of the NCS4 and/or NCS5 address space must be set as shown in Table 20-6 to enable the required access type. NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select mode on the corresponding Chip Select. 144 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these waveforms and timings, refer to the Static Memory Controller section. Table 20-6. Mode Attribute Memory CFCE1 and CFCE2 Truth Table CFCE2 NBS1 NBS1 CFCE1 NBS0 NBS0 0 NBS0 0 DBW 16 bits 16bits 8 bits 16 bits 8 bits Comment Access to Even Byte on D[7:0] Access to Even Byte on D[7:0] Access to Odd Byte on D[15:8] Access to Odd Byte on D[7:0] Access to Even Byte on D[7:0] Access to Odd Byte on D[15:8] Access to Odd Byte on D[7:0] Byte Select SMC Access Mode Byte Select Byte Select Common Memory 1 NBS1 I/O Mode 1 True IDE Mode Task File Data Register Alternate True IDE Mode Control Register Alternate Status Read Drive Address Standby Mode or Address Space is not assigned to CF 0 0 1 1 1 1 Don't Care 8 bits - 1 1 0 0 8 bits 16 bits Access to Even Byte on D[7:0] Access to Odd Byte on D[7:0] Access to Even Byte on D[7:0] Access to Odd Byte on D[15:8] Byte Select Access to Even Byte on D[7:0] Access to Odd Byte on D[7:0] - Don't Care - 20.6.6.3 Read/Write Signals In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deactivated. Likewise, in common memory mode and attribute memory mode, the SMC signals are driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. Figure 20-4 on page 146 demonstrates a schematic representation of this logic. Attribute memory mode, common memory mode and I/O mode are supported by setting the address setup and hold time on the NCS4 (and/or NCS5) chip select to the appropriate values. 145 6384D-ATARM-04-May-09 Figure 20-4. CompactFlash Read/Write Control Signals External Bus Interface SMC A23 1 1 0 1 A22 NRD_NOE NWR0_NWE 1 1 0 1 CompactFlash Logic 0 0 1 1 CFOE CFWE CFIOR CFIOW Table 20-7. CompactFlash Mode Selection CFOE NRD 1 0 CFWE NWR0_NWE 1 1 CFIOR 1 NRD NRD CFIOW 1 NWR0_NWE NWR0_NWE Mode Base Address Attribute Memory Common Memory I/O Mode True IDE Mode 20.6.6.4 Multiplexing of CompactFlash Signals on EBI Pins Table 20-8 on page 146 and Table 20-9 on page 147 illustrate the multiplexing of the CompactFlash logic signals with other EBI signals on the EBI pins. The EBI pins in Table 20-8 are strictly dedicated to the CompactFlash interface as soon as the EBI_CS4A and/or EBI_CS5A field of the EBI_CSA Register in the Chip Configuration User Interface is set. These pins must not be used to drive any other memory devices. The EBI pins in Table 20-9 on page 147 remain shared between all memory areas when the corresponding CompactFlash interface is enabled (EBI_CS4A = 1 and/or EBI_CS5A = 1). Table 20-8. Pins Dedicated CompactFlash Interface Multiplexing CompactFlash Signals CS4A = 1 CS5A = 1 CS4A = 0 NCS4 CFCS1 NCS5 EBI Signals CS5A = 0 NCS4/CFCS0 NCS5/CFCS1 CFCS0 146 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 20-9. Shared CompactFlash Interface Multiplexing Access to CompactFlash Device Access to Other EBI Devices EBI Signals NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 A25 Pins NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW A25/CFRNW CompactFlash Signals CFOE CFWE CFIOR CFIOW CFRNW 20.6.6.5 Application Example Figure 20-5 on page 148 illustrates an example of a CompactFlash application. CFCS0 and CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direction and the output enable of the buffers between the EBI and the CompactFlash Device. The timing of the CFCS0 signal is identical to the NCS4 signal. Moreover, the CFRNW signal remains valid throughout the transfer, as does the address bus. The CompactFlash _WAIT signal is connected to the NWAIT input of the Static Memory Controller. For details on these waveforms and timings, refer to the section "Static Memory Controller (SMC)". 147 6384D-ATARM-04-May-09 Figure 20-5. CompactFlash Application Example EBI CompactFlash Connector D[15:0] DIR /OE A25/CFRNW NCS4/CFCS0 D[15:0] _CD1 CD (PIO) _CD2 /OE A[10:0] A22/REG A[10:0] _REG NOE/CFOE NWE/CFWE NWR1/CFIOR NWR3/CFIOW _OE _WE _IORD _IOWR CFCE1 CFCE2 _CE1 _CE2 NWAIT _WAIT 20.6.7 NAND Flash Support The External Bus Interface integrates circuitry that interfaces to NAND Flash devices. External Bus Interface The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the EBI_CS3A field in the EBI_CSA Register in the Chip Configuration User Interface to the appropriate value enables the NAND Flash logic. For details on this register, refer to the section "AT91SAM9G20 Bus Matrix". Access to an external NAND Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF). The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the NCS3 address space. See Figure 20-6 on page 149 for more information. For details on the waveforms, refer to the section "Static Memory Controller (SMC)". 20.6.7.1 148 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 20-6. NAND Flash Signal Multiplexing on EBI Pins SMC NAND Flash Logic NCSx NRD_NOE NANDOE NANDOE NANDWE NWR0_NWE NANDWE 20.6.7.2 NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode. Figure 20-7. NAND Flash Application Example D[7:0] A[22:21] AD[7:0] ALE CLE NCSx/NANDCS Not Connected EBI NAND Flash NANDOE NANDWE NOE NWE PIO PIO CE R/B Note: The External Bus Interface is also able to support 16-bit devices. 149 6384D-ATARM-04-May-09 20.7 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 20.7.1 16-bit SDRAM Hardware Configuration D[0..15] A[0..14] (Not used A12) U1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A13 SDA10 BA0 BA1 A14 SDCKE SDCK 1%6 1%6 CAS RAS SDWE SDA10 BA0 BA1 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 SDCKE SDCK A0 CFIOR_NBS1_NWR1 CAS RAS SDWE SDCS_NCS1 37 38 15 39 17 18 16 19 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3V3 C1 C2 C3 C4 C5 C6 C7 1 1 1 1 1 1 1 TSOP54 PACKAGE 256 Mbits 20.7.1.1 Software Configuration The following configuration has to be performed: * Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space. * Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits. The SDRAM initialization sequence is described in the "SDRAM device initialization" part of the SDRAM controller. 150 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 20.7.2 20.7.2.1 D[0..31] A[0..14] 32-bit SDRAM Hardware Configuration (Not used A12) U1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A13 SDA10 BA0 BA1 A14 SDCKE SDCK 1%6 1%6 CAS RAS SDWE SDA10 BA0 BA1 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 SDCKE SDCK A0 CFIOR_NBS1_NWR1 CAS RAS SDWE 37 38 15 39 17 18 16 19 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3V3 C1 C2 C3 C4 C5 C6 C7 100NF 100NF 100NF 100NF 100NF 100NF 100NF A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDA10 A13 BA0 BA1 A14 SDCKE SDCK A1 CFIOW_NBS3_NWR3 1%6 1%6 CAS RAS SDWE 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 37 38 15 39 17 18 16 19 U2 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 3V3 C8 C9 C10 C11 C12 C13 C14 100NF 100NF 100NF 100NF 100NF 100NF 100NF SDCS_NCS1 256 Mbits TSOP54 PACKAGE 256 Mbits 20.7.2.2 Software Configuration The following configuration has to be performed: * Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space. * Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. The SDRAM initialization sequence is described in the "SDRAM device initialization" part of the SDRAM controller. 151 6384D-ATARM-04-May-09 20.7.3 8-bit NAND Flash Figure 20-8. Hardware Configuration D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 3V3 R1 R2 10K 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 16 17 8 18 9 7 19 CLE ALE RE WE CE R/B WP N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C K9F2G08U0M I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.C VCC VCC VSS VSS 29 30 31 32 41 42 43 44 48 47 46 45 40 39 38 35 34 33 28 27 37 12 36 13 D0 D1 D2 D3 D4 D5 D6 D7 3V3 C2 100NF C1 100NF TSOP48 PACKAGE 2 Gb 20.7.3.1 Software Configuration The following configuration has to be performed: * Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register located in the bus matrix memory space * Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled respectively by setting to 1 the address bit A21 and A22 during accesses. * Configure a PIO line as an input to manage the Ready/Busy signal. * Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. 152 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 20.7.4 16-bit NAND Flash Figure 20-9. Hardware Configuration D[0..15] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 3V3 R1 R2 10K 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 16 17 8 18 9 7 19 CLE ALE RE WE CE R/B WP N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C MT29F2G16AABWP-ET I/O0 26 I/O1 28 I/O2 30 I/O3 32 I/O4 40 I/O5 42 I/O6 44 I/O7 46 I/O8 27 I/O9 29 I/O10 31 I/O11 33 I/O12 41 I/O13 43 I/O14 45 I/O15 47 N.C PRE N.C VCC VCC VSS VSS VSS 39 38 36 37 12 48 25 13 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3V3 C2 100NF C1 100NF TSOP48 PACKAGE 2 Gb 20.7.4.1 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except the data bus width programmed in the mode register of the Static Memory Controller. 153 6384D-ATARM-04-May-09 20.7.5 NOR Flash on NCS0 Figure 20-10. Hardware Configuration D[0..15] A[1..22] U1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 10 9 12 11 14 13 26 28 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 RESET WE WP VPP CE OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 AT49BV6416 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3V3 NRST NWE 3V3 NCS0 NRD VCCQ VCC VSS VSS 47 37 46 27 C2 100NF TSOP48 PACKAGE 20.7.5.1 C1 100NF Software Configuration The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. 154 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 20.7.6 20.7.6.1 Compact Flash Hardware Configuration D[0..15] MN1A D15 D14 D13 D12 D11 D10 D9 D8 MEMORY & I/O MODE J1 3V3 C1 100NF C2 100NF A2 A1 B2 B1 C2 C1 D2 D1 A3 A4 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1DIR 1OE 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 A5 A6 B5 B6 C5 C6 D5 D6 CF_D15 CF_D14 CF_D13 CF_D12 CF_D11 CF_D10 CF_D9 CF_D8 74ALVCH32245 MN1B D7 D6 D5 D4 D3 D2 D1 D0 A25/CFRNW CFCSx (CFCS0 or CFCS1) (ANY PIO) &$5' '(7(&7 A[0..10] MN1C A10 A9 A8 A7 A6 A5 A4 A3 3V3 E2 E1 F2 F1 G2 G1 H2 H1 H3 H4 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2DIR 2OE 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 E5 E6 F5 F6 G5 G6 H5 H6 CF_D7 CF_D6 CF_D5 CF_D4 CF_D3 CF_D2 CF_D1 CF_D0 CF_D15 CF_D14 CF_D13 CF_D12 CF_D11 CF_D10 CF_D9 CF_D8 CF_D7 CF_D6 CF_D5 CF_D4 CF_D3 CF_D2 CF_D1 CF_D0 CD2 CD1 CF_A10 CF_A9 CF_A8 CF_A7 CF_A6 CF_A5 CF_A4 CF_A3 CF_A2 CF_A1 CF_A0 REG 31 30 29 28 27 49 48 47 6 5 4 3 2 23 22 21 25 26 8 10 11 12 14 15 16 17 18 19 20 44 36 9 35 34 32 7 24 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CD2# CD1# A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 REG# WE# OE# IOWR# IORD# CE2# CE1# WP WAIT# RESET VCC VCC GND GND 38 13 50 1 3V3 4 6 5 74ALVCH32245 MN2B SN74ALVC32 R1 MN2A 47K SN74ALVC32 R2 47K CD2 CD1 1 2 3 J5 J6 K5 K6 L5 L6 M5 M6 J3 J4 3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8 3DIR 3OE 3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8 J2 J1 K2 K1 L2 L1 M2 M1 CF_A10 CF_A9 CF_A8 CF_A7 CF_A6 CF_A5 CF_A4 CF_A3 WE OE IOWR IORD CE2 CE1 CSEL# INPACK# BVD2 BVD1 39 43 45 46 WAIT# RESET 42 41 VS2# VS1# RDY/BSY 40 33 37 RDY/BSY 74ALVCH32245 MN1D A2 A1 A0 A22/REG CFWE CFOE CFIOW CFIOR N5 N6 P5 P6 R5 R6 T6 T5 T3 T4 4A1 4A2 4A3 4A4 4A5 4A6 4A7 4A8 4DIR 4OE 4B1 4B2 4B3 4B4 4B5 4B6 4B7 4B8 N2 N1 P2 P1 R2 R1 T1 T2 CF_A2 CF_A1 CF_A0 REG WE OE IOWR IORD N7E50-7516VY-20 74ALVCH32245 1 CFCE2 2 MN3A SN74ALVC125 3 CE2 4 CFCE1 5 MN3B SN74ALVC125 6 CE1 10 (ANY PIO) CFRST 9 MN3C SN74ALVC125 RESET 8 13 (ANY PIO) CFIRQ 11 MN3D R3 SN74ALVC125 10K RDY/BSY 12 3V3 MN4 3V3 NWAIT 5 VCC 4 1 2 3 WAIT# R4 10K 3V3 GND SN74LVC1G125-Q1 155 6384D-ATARM-04-May-09 20.7.6.2 Software Configuration The following configuration has to be performed: * Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located in the bus matrix memory space. * The address line A23 is to select I/O (A23=1) or Memory mode (A23=0) and the address line A22 for REG function. * A23, CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. * Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. * Configure SMC CS4 and/or SMC_CS5 (for Slot 0 or 1) Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. 156 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 20.7.7 20.7.7.1 Compact Flash True IDE Hardware Configuration D[0..15] MN1A D15 D14 D13 D12 D11 D10 D9 D8 TRUE IDE MODE J1 3V3 A2 A1 B2 B1 C2 C1 D2 D1 A3 A4 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1DIR 1OE 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 A5 A6 B5 B6 C5 C6 D5 D6 CF_D15 CF_D14 CF_D13 CF_D12 CF_D11 CF_D10 CF_D9 CF_D8 74ALVCH32245 MN1B D7 D6 D5 D4 D3 D2 D1 D0 A25/CFRNW CFCSx (CFCS0 or CFCS1) (ANY PIO) &$5' '(7(&7 A[0..10] A10 A9 A8 A7 A6 A5 A4 A3 3V3 MN1C CF_A10 CF_A9 CF_A8 CF_A7 CF_A6 CF_A5 CF_A4 CF_A3 E2 E1 F2 F1 G2 G1 H2 H1 H3 H4 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2DIR 2OE 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 E5 E6 F5 F6 G5 G6 H5 H6 CF_D7 CF_D6 CF_D5 CF_D4 CF_D3 CF_D2 CF_D1 CF_D0 CF_D15 CF_D14 CF_D13 CF_D12 CF_D11 CF_D10 CF_D9 CF_D8 CF_D7 CF_D6 CF_D5 CF_D4 CF_D3 CF_D2 CF_D1 CF_D0 CD2 CD1 31 30 29 28 27 49 48 47 6 5 4 3 2 23 22 21 25 26 8 10 11 12 14 15 16 17 18 19 20 44 36 9 35 34 32 7 24 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CD2# CD1# A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 REG# WE# ATA SEL# IOWR# IORD# CS1# CS0# IOIS16# IORDY RESET# N7E50-7516VY-20 VCC VCC GND GND 38 13 50 1 C1 100NF C2 100NF 3V3 4 6 5 74ALVCH32245 MN2B SN74ALVC32 R1 MN2A 47K SN74ALVC32 R2 47K CD2 CD1 CF_A2 CF_A1 CF_A0 3V3 1 2 3 J5 J6 K5 K6 L5 L6 M5 M6 J3 J4 3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8 3DIR 3OE 3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8 J2 J1 K2 K1 L2 L1 M2 M1 CSEL# INPACK# DASP# PDIAG# 39 43 45 46 IOWR IORD CE2 CE1 IORDY RESET# 42 41 VS2# VS1# INTRQ 40 33 37 INTRQ 74ALVCH32245 MN1D A2 A1 A0 A22/REG CFWE CFOE CFIOW CFIOR N5 N6 P5 P6 R5 R6 T6 T5 T3 T4 4A1 4A2 4A3 4A4 4A5 4A6 4A7 4A8 4DIR 4OE 4B1 4B2 4B3 4B4 4B5 4B6 4B7 4B8 N2 N1 P2 P1 R2 R1 T1 T2 CF_A2 CF_A1 CF_A0 REG WE OE IOWR IORD 74ALVCH32245 1 CFCE2 2 MN3A SN74ALVC125 3 CE2 4 CFCE1 5 10 MN3B SN74ALVC125 6 CE1 (ANY PIO) CFRST 9 13 MN3C SN74ALVC125 RESET# 8 (ANY PIO) CFIRQ 11 MN3D SN74ALVC125 INTRQ 12 R3 10K 3V3 MN4 3V3 NWAIT 5 VCC 4 1 2 3 IORDY R4 10K 3V3 GND SN74LVC1G125-Q1 157 6384D-ATARM-04-May-09 20.7.7.2 Software Configuration The following configuration has to be performed: * Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located in the bus matrix memory space. * The address line A21 is to select Alternate True IDE (A21=1) or True IDE (A21=0) modes. * CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. * Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. * Configure SMC CS4 and/or SMC_CS5 (for Slot 0 or 1) Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. 158 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 21. Static Memory Controller (SMC) 21.1 Overview The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable. The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from userprogrammed waveforms to slow-rate specific waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for page size up to 32 bytes. 21.2 I/O Lines Description I/O Line Description Description Static Memory Controller Chip Select Lines Read Signal Write 0/Write Enable Signal Address Bit 0/Byte 0 Select Signal Write 1/Byte 1 Select Signal Address Bit 1/Write 2/Byte 2 Select Signal Write 3/Byte 3 Select Signal Address Bus Data Bus External Wait Signal Type Output Output Output Output Output Output Output Output I/O Input Low Active Level Low Low Low Low Low Low Low Table 21-1. Name NCS[7:0] NRD NWR0/NWE A0/NBS0 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 A[25:2] D[31:0] NWAIT 21.3 Multiplexed Signals Static Memory Controller (SMC) Multiplexed Signals Related Function Byte-write or byte-select access, see "Byte Write or Byte Select Access" on page 161 8-bit or 16-/32-bit data bus, see "Data Bus Width" on page 161 Byte-write or byte-select access see "Byte Write or Byte Select Access" on page 161 NBS2 8-/16-bit or 32-bit data bus, see "Data Bus Width" on page 161. Byte-write or byte-select access, see "Byte Write or Byte Select Access" on page 161 Byte-write or byte-select access see "Byte Write or Byte Select Access" on page 161 Table 21-2. Multiplexed Signals NWR0 A0 NWR1 A1 NWR3 NWE NBS0 NBS1 NWR2 NBS3 159 6384D-ATARM-04-May-09 21.4 21.4.1 Application Example Hardware Interface Figure 21-1. SMC Connections to Static Memory Devices D0-D31 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 D0 - D7 128K x 8 SRAM D0 - D7 CS A0 - A16 A2 - A18 D8-D15 128K x 8 SRAM D0-D7 CS A0 - A16 A2 - A18 NCS0 NCS1 NCS2 NCS3 NCS4 NCS5 NCS6 NCS7 NRD NWR0/NWE OE WE NRD NWR1/NBS1 OE WE D16 - D23 A2 - A25 CS 128K x 8 SRAM D0 - D7 D24-D31 128K x 8 SRAM D0-D7 CS A2 - A18 A0 - A16 A0 - A16 NRD A1/NWR2/NBS2 OE WE A2 - A18 NRD OE NWR3/NBS3 WE Static Memory Controller 21.5 21.5.1 Product Dependencies I/O Lines The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. 160 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 21.6 External Memory Mapping The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 21-2). A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for 32-bit memory. Figure 21-2. Memory Connections for Eight External Devices NCS[0] - NCS[7] NRD NCS7 NCS6 NCS5 NCS4 NCS3 NCS2 NCS1 NCS0 Memory Enable Memory Enable SMC NWE A[25:0] D[31:0] Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable A[25:0] 8 or 16 or 32 D[31:0] or D[15:0] or D[7:0] 21.7 21.7.1 Connection to External Devices Data Bus Width A data bus width of 8, 16, or 32 bits can be selected for each chip select. This option is controlled by the field DBW in SMC_MODE (Mode Register) for the corresponding chip select. Figure 21-3 shows how to connect a 512K x 8-bit memory on NCS2. Figure 21-4 shows how to connect a 512K x 16-bit memory on NCS2. Figure 21-5 shows two 16-bit memories connected as a single 32-bit memory 21.7.2 Byte Write or Byte Select Access Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access. This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. 161 6384D-ATARM-04-May-09 Figure 21-3. Memory Connection for an 8-bit Data Bus D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] D[7:0] A[18:2] A0 A1 Write Enable Output Enable Memory Enable Figure 21-4. Memory Connection for a 16-bit Data Bus D[15:0] A[19:2] A1 SMC NBS0 NBS1 NWE NRD NCS[2] D[15:0] A[18:1] A[0] Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable Figure 21-5. Memory Connection for a 32-bit Data Bus D[31:16] D[15:0] A[20:2] D[31:16] D[15:0] A[18:0] Byte 0 Enable Byte 1 Enable Byte 2 Enable Byte 3 Enable Write Enable Output Enable Memory Enable SMC NBS0 NBS1 NBS2 NBS3 NWE NRD NCS[2] 162 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 21.7.2.1 Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. * For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory. * For 32-bit devices: NWR0, NWR1, NWR2 and NWR3, are the write signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. One single read signal (NRD) is provided. Byte Write Access is used to connect 4 x 8-bit devices as a 32-bit memory. Byte Write option is illustrated on Figure 21-6. 21.7.2.2 Byte Select Access In this mode, read/write operations can be enabled/disabled at a byte level. One byte-select line per byte of the data bus is provided. One NRD and one NWE signal control read and write. * For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. Byte Select Access is used to connect one 16-bit device. * For 32-bit devices: NBS0, NBS1, NBS2 and NBS3, are the selection signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. Byte Select Access is used to connect two 16-bit devices. Figure 21-7 shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access mode, on NCS3 (BAT = Byte Select Access). 163 6384D-ATARM-04-May-09 Figure 21-6. Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option D[7:0] D[15:8] A[24:2] A[23:1] A[0] Write Enable Read Enable Memory Enable D[7:0] SMC A1 NWR0 NWR1 NRD NCS[3] D[15:8] A[23:1] A[0] Write Enable Read Enable Memory Enable 21.7.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 21-3 shows signal multiplexing depending on the data bus width and the byte access type. For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused. 164 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 21-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option) D[15:0] D[31:16] A[25:2] NWE NBS0 NBS1 A[23:0] Write Enable Low Byte Enable High Byte Enable D[15:0] SMC NBS2 NBS3 NRD NCS[3] Read Enable Memory Enable D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable Table 21-3. Signal Name Device Type SMC Multiplexed Signal Translation 32-bit Bus 1x32-bit Byte Select NBS0 NWE NBS1 NBS2 NBS3 2x16-bit Byte Select NBS0 NWE NBS1 NBS2 NBS3 NWR0 NWR1 NWR2 NWR3 4 x 8-bit Byte Write 16-bit Bus 1x16-bit Byte Select NBS0 NWE NBS1 A1 NWR0 NWR1 A1 A1 2 x 8-bit Byte Write A0 NWE 8-bit Bus 1 x 8-bit Byte Access Type (BAT) NBS0_A0 NWE_NWR0 NBS1_NWR1 NBS2_NWR2_A1 NBS3_NWR3 21.8 Standard Read and Write Protocols In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..7] chip select lines. 165 6384D-ATARM-04-May-09 21.8.1 Read Waveforms The read cycle is shown on Figure 21-8. The read cycle starts with the address setting on the memory address bus, i.e.: {A[25:2], A1, A0} for 8-bit devices {A[25:2], A1} for 16-bit devices A[25:2] for 32-bit devices. Figure 21-8. Standard Read Cycle MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] NRD_SETUP NRD_PULSE NRD_HOLD NCS_RD_SETUP NCS_RD_PULSE NRD_CYCLE NCS_RD_HOLD 21.8.1.1 NRD Waveform The NRD signal is characterized by a setup timing, a pulse width and a hold timing. 1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge. 166 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 21.8.1.2 NCS Waveform Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. 21.8.1.3 Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NRD and NCS timings are coherent, user must define the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as: NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE 21.8.1.4 Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see Figure 21-9). 167 6384D-ATARM-04-May-09 Figure 21-9. No Setup, No Hold On NRD and NCS Read Signals MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] NRD_PULSE NRD_PULSE NRD_PULSE NCS_RD_PULSE NCS_RD_PULSE NCS_RD_PULSE NRD_CYCLE NRD_CYCLE NRD_CYCLE 21.8.1.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 21.8.2 Read Mode As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal of NRD and NCS controls the read operation. 21.8.2.1 Read is Controlled by NRD (READ_MODE = 1): Figure 21-10 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available tPACC after the falling edge of NRD, and turns to `Z' after the rising edge of NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the programmed waveform of NCS may be. 168 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 21-10. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS tPACC D[31:0] Data Sampling 21.8.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 21-11 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may be. Figure 21-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS tPACC D[31:0] Data Sampling 169 6384D-ATARM-04-May-09 21.8.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 21-12. The write cycle starts with the address setting on the memory address bus. NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge; 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge; 3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after the NWE rising edge. The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3. 21.8.3.1 21.8.3.2 NCS Waveforms The NCS signal waveforms in write operation are not the same that those applied in read operations, but are separately defined: 1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 21-12. Write Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NCS NWE_SETUP NCS_WR_SETUP NWE_PULSE NWE_HOLD NCS_WR_PULSE NWE_CYCLE NCS_WR_HOLD 170 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 21.8.3.3 Write Cycle The write-cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to: NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as: NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE 21.8.3.4 Null Delay Setup and Hold If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 21-13). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed. Figure 21-13. Null Setup and Hold Values of NCS and NWE in Write Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] NWE_PULSE NWE_PULSE NWE_PULSE NCS_WR_PULSE NCS_WR_PULSE NCS_WR_PULSE NWE_CYCLE NWE_CYCLE NWE_CYCLE 21.8.3.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior. 171 6384D-ATARM-04-May-09 21.8.4 Write Mode The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal controls the write operation. 21.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1): Figure 21-14 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are turned out after the NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS. Figure 21-14. WRITE_MODE = 1. The write operation is controlled by NWE MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 21.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 21-15 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. 172 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 21-15. WRITE_MODE = 0. The write operation is controlled by NCS MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 21.8.5 Coding Timing Parameters All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to their type. The SMC_SETUP register groups the definition of all setup parameters: * NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP The SMC_PULSE register groups the definition of all pulse parameters: * NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE The SMC_CYCLE register groups the definition of all cycle parameters: * NRD_CYCLE, NWE_CYCLE Table 21-4 shows how the timing parameters are coded and their permitted range. Table 21-4. Coding and Range of Timing Parameters Permitted Range Coded Value setup [5:0] pulse [6:0] cycle [8:0] Number of Bits 6 7 9 Effective Value 128 x setup[5] + setup[4:0] 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0] Coded Value 0 31 0 63 0 127 Effective Value 128 128+31 256 256+63 256 256+127 512 512+127 768 768+127 173 6384D-ATARM-04-May-09 21.8.6 Reset Values of Timing Parameters Table 21-5 gives the default value of timing parameters at reset. Table 21-5. Register SMC_SETUP SMC_PULSE SMC_CYCLE WRITE_MODE READ_MODE Reset Values of Timing Parameters Reset Value 0x00000000 0x01010101 0x00010001 1 1 All setup timings are set to 1 All pulse timings are set to 1 The read and write operation last 3 Master Clock cycles and provide one hold cycle Write is controlled with NWE Read is controlled with NRD 21.8.7 Usage Restriction The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC. For read operations: Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, NCS and NRD signals. For write operations: If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See "Early Read Wait State" on page 175. For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus. 21.9 Automatic Wait States Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict. 21.9.1 Chip Select Wait States The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..7], NRD lines are all set to 1. Figure 21-16 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2. 174 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 21-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWE NCS0 NCS2 NRD_CYCLE D[31:0] NWE_CYCLE Read to Write Chip Select Wait State Wait State 21.9.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select). An early read wait state is automatically inserted if at least one of the following conditions is valid: * if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 21-18). * in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode (Figure 21-19). The write operation must end with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly. * in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See Figure 21-20. Figure 21-17. 175 6384D-ATARM-04-May-09 Figure 21-18. Early Read Wait State: Write with No Hold Followed by Read with No Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NRD no hold no setup D[31:0] write cycle Early Read wait state read cycle Figure 21-19. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD no hold D[31:0] no setup write cycle (WRITE_MODE = 0) Early Read wait state read cycle (READ_MODE = 0 or READ_MODE = 1) 176 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 21-20. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 internal write controlling signal external write controlling signal (NWE) no hold NRD read setup = 1 D[31:0] write cycle (WRITE_MODE = 1) Early Read wait state read cycle (READ_MODE = 0 or READ_MODE = 1) 21.9.3 Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface. When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called "Reload User Configuration Wait State" is used by the SMC to load the new set of parameters to apply to next accesses. The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before and after re-programming the user interface are made to different devices (Chip Selects), then one single Chip Select Wait State is applied. On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload Configuration Wait State is inserted, even if the change does not concern the current Chip Select. 21.9.3.1 User Procedure To insert a Reload Configuration Wait State, the SMC detects a write access to any SMC_MODE register of the user interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in the user interface, he must validate the modification by writing the SMC_MODE, even if no change was made on the mode parameters. Slow Clock Mode Transition A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see "Slow Clock Mode" on page 189). 21.9.3.2 177 6384D-ATARM-04-May-09 21.9.4 Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See Figure 21-16 on page 175. 178 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 21.10 Data Float Wait States Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access: * before starting a read access to a different external memory * before starting a write access to the same device or to a different external one. The Data Float Output Time (t DF ) for each external memory device is programmed in the TDF_CYCLES field of the SMC_MODE register for the corresponding chip select. The value of TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long t DF will not slow down the execution of a program from internal memory. The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the SMC_MODE register for the corresponding chip select. 21.10.1 READ_MODE Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts TDF_CYCLES MCK cycles. When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS. Figure 21-21 illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), assuming a data float period of 2 cycles (TDF_CYCLES = 2). Figure 21-22 shows the read operation when controlled by NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3. 179 6384D-ATARM-04-May-09 Figure 21-21. TDF Period in NRD Controlled Read Access (TDF = 2) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NRD NCS tpacc D[31:0] TDF = 2 clock cycles NRD controlled read operation Figure 21-22. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NCS tpacc D[31:0] TDF = 3 clock cycles NCS controlled read operation 180 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 21.10.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 21-23 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with: NRD_HOLD = 4; READ_MODE = 1 (NRD controlled) NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled) TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled). Figure 21-23. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins MCK A[25:2] NRD NRD_HOLD= 4 NWE NWE_SETUP= 3 NCS0 TDF_CYCLES = 6 D[31:0] read access on NCS0 (NRD controlled) Read to Write Wait State write access on NCS0 (NWE controlled) 21.10.3 TDF Optimization Disabled (TDF_MODE = 0) When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait states will be inserted. Figure 21-24, Figure 21-25 and Figure 21-26 illustrate the cases: * read access followed by a read access on another chip select, * read access followed by a write access on another chip select, * read access followed by a write access on the same chip select, with no TDF optimization. 181 6384D-ATARM-04-May-09 Figure 21-24. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read1 hold = 1 read2 setup = 1 read2 controlling signal (NRD) D[31:0] TDF_CYCLES = 6 5 TDF WAIT STATES read1 cycle TDF_CYCLES = 6 Chip Select Wait State read 2 cycle TDF_MODE = 0 (optimization disabled) Figure 21-25. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read1 hold = 1 write2 setup = 1 write2 controlling signal (NWE) TDF_CYCLES = 4 D[31:0] read1 cycle TDF_CYCLES = 4 Read to Write Chip Select Wait State Wait State 2 TDF WAIT STATES write2 cycle TDF_MODE = 0 (optimization disabled) 182 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 21-26. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read1 hold = 1 write2 setup = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[31:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 write2 cycle TDF_MODE = 0 (optimization disabled) Read to Write Wait State 21.11 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be set to either to "10" (frozen mode) or "11" (ready mode). When the EXNW_MODE is set to "00" (disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select. 21.11.1 Restriction When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Page Mode ("Asynchronous Page Mode" on page 192), or in Slow Clock Mode ("Slow Clock Mode" on page 189). The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior. 183 6384D-ATARM-04-May-09 21.11.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 2127. This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC. The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 21-28. Figure 21-27. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 NCS 5 4 3 2 2 3 2 1 1 FROZEN STATE 1 1 0 2 2 1 0 D[31:0] NWAIT internally synchronized NWAIT signal Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 184 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 21-28. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 4 3 2 FROZEN STATE 2 2 1 0 2 1 0 5 5 5 4 3 2 1 0 1 0 NCS NRD NWAIT internally synchronized NWAIT signal Read cycle EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 Assertion is ignored 185 6384D-ATARM-04-May-09 21.11.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 21-29 and Figure 21-30. After deassertion, the access is completed: the hold step of the access is performed. This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation. If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in Figure 21-30. Figure 21-29. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 Wait STATE 4 3 2 1 0 0 0 NWE 6 NCS 5 4 3 2 1 1 1 0 D[31:0] NWAIT internally synchronized NWAIT signal Write cycle EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 186 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 21-30. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 6 NCS 5 4 3 2 1 0 Wait STATE 0 NRD 6 5 4 3 2 1 1 0 NWAIT internally synchronized NWAIT signal Read cycle EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE =7 Assertion is ignored 187 6384D-ATARM-04-May-09 21.11.4 NWAIT Latency and Read/write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on Figure 21-31. When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write controlling signal of at least: minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle Figure 21-31. NWAIT Latency MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 4 NRD minimal pulse length 3 2 1 0 0 WAIT STATE 0 NWAIT intenally synchronized NWAIT signal NWAIT latency 2 cycle resynchronization Read cycle EXNW_MODE = 10 or 11 READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 188 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 21.12 Slow Clock Mode The SMC is able to automatically apply a set of "slow clock mode" read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate. When activated, the slow mode is active on all chip selects. 21.12.1 Slow Clock Mode Waveforms Figure 21-32 illustrates the read and write operations in slow clock mode. They are valid on all chip selects. Table 21-6 indicates the value of read and write parameters in slow clock mode. Figure 21-32. Read/write Cycles in Slow Clock Mode MCK MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD 1 1 NCS NRD_CYCLE = 2 SLOW CLOCK MODE READ NWE 1 1 1 NCS NWE_CYCLE = 3 SLOW CLOCK MODE WRITE Table 21-6. Read and Write Timing Parameters in Slow Clock Mode Duration (cycles) 1 1 0 2 2 Write Parameters NWE_SETUP NWE_PULSE NCS_WR_SETUP NCS_WR_PULSE NWE_CYCLE Duration (cycles) 1 1 0 3 3 Read Parameters NRD_SETUP NRD_PULSE NCS_RD_SETUP NCS_RD_PULSE NRD_CYCLE 189 6384D-ATARM-04-May-09 21.12.2 Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.See Figure 21-33 on page 190. The external device may not be fast enough to support such timings. Figure 21-34 illustrates the recommended procedure to properly switch from one mode to the other. Figure 21-33. Clock Rate Transition Occurs while the SMC is Performing a Write Operation Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS 1 1 1 1 1 2 3 2 NWE_CYCLE = 3 SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE NWE_CYCLE = 7 NORMAL MODE WRITE This write cycle finishes with the slow clock mode set of parameters after the clock rate transition Slow clock mode transition is detected: Reload Configuration Wait State 190 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 21-34. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS 1 1 2 3 2 SLOW CLOCK MODE WRITE IDLE STATE NORMAL MODE WRITE Reload Configuration Wait State 191 6384D-ATARM-04-May-09 21.13 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the page in memory, the LSB of address define the address of the data in the page as detailed in Table 21-7. With page mode memory devices, the first access to one page (tpa) takes longer than the subsequent accesses to the page (tsa ) as shown in Figure 21-35. When in page mode, the SMC enables the user to define different read timings for the first access within one page, and next accesses within the page. Table 21-7. Page Size 4 bytes 8 bytes 16 bytes 32 bytes Notes: Page Address and Data Address within a Page Page Address(1) A[25:2] A[25:3] A[25:4] A[25:5] Data Address in the Page(2) A[1:0] A[2:0] A[3:0] A[4:0] 1. A denotes the address bus of the memory device 2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored. 21.13.1 Protocol and Timings in Page Mode Figure 21-35 shows the NRD and NCS timings in page mode access. Figure 21-35. Page Mode Read Protocol (Address MSB and LSB are defined in Table 21-7) MCK A[MSB] A[LSB] NRD NCS tpa tsa tsa D[31:0] NCS_RD_PULSE NRD_PULSE NRD_PULSE The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS 192 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary timings are identical. The pulse length of the first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses within the page are defined using the NRD_PULSE parameter. In page mode, the programming of the read timings is described in Table 21-8: Table 21-8. Parameter READ_MODE NCS_RD_SETUP NCS_RD_PULSE NRD_SETUP NRD_PULSE NRD_CYCLE Programming of Read Timings in Page Mode Value `x' `x' tpa `x' tsa `x' Definition No impact No impact Access time of first access to the page No impact Access time of subsequent accesses in the page No impact The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page access timing (tpa) and the NRD_PULSE for accesses to the page (tsa), even if the programmed value for tpa is shorter than the programmed value for tsa. 21.13.2 Byte Access Type in Page Mode The Byte Access Type configuration remains active in page mode. For 16-bit or 32-bit page mode devices that require byte selection signals, configure the BAT field of the SMC_REGISTER to 0 (byte select access type). Page Mode Restriction The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may lead to unpredictable behavior. Sequential and Non-sequential Accesses If the chip select and the MSB of addresses as defined in Table 21-7 are identical, then the current access lies in the same page as the previous one, and no page break occurs. Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (tsa). Figure 21-36 illustrates access to an 8-bit memory device in page mode, with 8-byte pages. Access to D1 causes a page access with a long access time (tpa). Accesses to D3 and D7, though they are not sequential accesses, only require a short access time (tsa). If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip select is different from the previous access, a page break occurs. If two sequential accesses are made to the page mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses. 21.13.3 21.13.4 193 6384D-ATARM-04-May-09 Figure 21-36. Access to Non-sequential Data within the Same Page MCK A[25:3] Page address A[2], A1, A0 A1 A3 A7 NRD NCS D[7:0] NCS_RD_PULSE D1 NRD_PULSE D3 NRD_PULSE D7 194 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 21.14 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 21-9. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 21-9, "CS_number" denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 21-9. Register Mapping Offset 0x10 x CS_number + 0x00 0x10 x CS_number + 0x04 0x10 x CS_number + 0x08 0x10 x CS_number + 0x0C Register SMC Setup Register SMC Pulse Register SMC Cycle Register SMC Mode Register Name SMC_SETUP SMC_PULSE SMC_CYCLE SMC_MODE Access Read-write Read-write Read-write Read-write Reset 0x00000000 0x01010101 0x00010001 0x10001000 195 6384D-ATARM-04-May-09 21.14.1 SMC Setup Register Register Name:SMC_SETUP[0 ..7] Access Type:Read-write 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 28 27 26 25 24 NCS_RD_SETUP 21 20 19 NRD_SETUP 13 12 11 10 9 8 18 17 16 NCS_WR_SETUP 5 4 3 NWE_SETUP 2 1 0 * NWE_SETUP: NWE Setup Length The NWE signal setup length is defined as: NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles * NCS_WR_SETUP: NCS Setup Length in WRITE Access In write access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles * NRD_SETUP: NRD Setup Length The NRD signal setup length is defined in clock cycles as: NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles * NCS_RD_SETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles 196 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 21.14.2 SMC Pulse Register Register Name:SMC_PULSE[0..7] Access Type:Read-write 31 - 23 - 15 - 7 - 30 29 28 27 NCS_RD_PULSE 26 25 24 22 21 20 19 NRD_PULSE 18 17 16 14 13 12 11 NCS_WR_PULSE 10 9 8 6 5 4 3 NWE_PULSE 2 1 0 * NWE_PULSE: NWE Pulse Length The NWE signal pulse length is defined as: NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles The NWE pulse length must be at least 1 clock cycle. * NCS_WR_PULSE: NCS Pulse Length in WRITE Access In write access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle. * NRD_PULSE: NRD Pulse Length In standard read access, the NRD signal pulse length is defined in clock cycles as: NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles The NRD pulse length must be at least 1 clock cycle. In page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the page. * NCS_RD_PULSE: NCS Pulse Length in READ Access In standard read access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle. In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page. 197 6384D-ATARM-04-May-09 21.14.3 SMC Cycle Register Register Name:SMC_CYCLE[0..7] Access Type:Read-write 31 - 23 30 - 22 29 - 21 28 - 20 NRD_CYCLE 27 - 19 26 - 18 25 - 17 24 NRD_CYCLE 16 15 - 7 14 - 6 13 - 5 12 - 4 NWE_CYCLE 11 - 3 10 - 2 9 - 1 8 NWE_CYCLE 0 * NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and hold steps of the NWE and NCS signals. It is defined as: Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles * NRD_CYCLE: Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals. It is defined as: Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles 198 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 21.14.4 SMC MODE Register Register Name:SMC_MODE[0..7] Access Type:Read-write 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 5 EXNW_MODE 21 - 13 DBW 4 29 PS 20 TDF_MODE 12 11 - 3 - 10 - 2 - 28 27 - 19 26 - 18 TDF_CYCLES 9 - 1 WRITE_MODE 8 BAT 0 READ_MODE 25 - 17 24 PMEN 16 * READ_MODE: 1: The read operation is controlled by the NRD signal. - If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD. - If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD. 0: The read operation is controlled by the NCS signal. - If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS. - If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS. * WRITE_MODE 1: The write operation is controlled by the NWE signal. - If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE. 0: The write operation is controlled by the NCS signal. - If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS. * EXNW_MODE: NWAIT Mode The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the read and write controlling signal. EXNW_MODE 0 0 1 1 0 1 0 1 NWAIT Mode Disabled Reserved Frozen Mode Ready Mode * Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select. * Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. * Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. 199 6384D-ATARM-04-May-09 * BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. * 1: Byte write access type: - Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3. - Read operation is controlled using NCS and NRD. * 0: Byte select access type: - Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3 - Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3 * DBW: Data Bus Width DBW 0 0 1 1 0 1 0 1 Data Bus Width 8-bit bus 16-bit bus 32-bit bus Reserved * TDF_CYCLES: Data Float Time This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set. * TDF_MODE: TDF Optimization 1: TDF optimization is enabled. - The number of TDF wait states is optimized using the setup period of the next read/write access. 0: TDF optimization is disabled. - The number of TDF wait states is inserted before the next access begins. * PMEN: Page Mode Enabled 1: Asynchronous burst read in page mode is applied on the corresponding chip select. 0: Standard read is applied. * PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes. PS 0 0 1 1 0 1 0 1 Page Size 4-byte page 8-byte page 16-byte page 32-byte page 200 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 22. SDRAM Controller (SDRAMC) 22.1 Overview The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAM Controller supports a read or write burst length of one location. It keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank. The SDRAM controller supports a CAS latency of 1, 2 or 3 and optimizes the read access depending on the frequency. The different modes available - self-refresh, power-down and deep power-down modes - minimize power consumption on the SDRAM device. 22.2 I/O Lines Description Table 22-1. Name SDCK SDCKE SDCS BA[1:0] RAS CAS SDWE NBS[3:0] SDRAMC_A[12:0] D[31:0] I/O Line Description Description SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select Signals Row Signal Column Signal SDRAM Write Enable Data Mask Enable Signals Address Bus Data Bus Type Output Output Output Output Output Output Output Output Output I/O Low Low Low Low High Low Active Level 201 6384D-ATARM-04-May-09 22.3 22.3.1 Application Example Software Interface The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller allows mapping different memory types according to the values set in the SDRAMC configuration register. The SDRAM Controller's function is to make the SDRAM device access protocol transparent to the user. Table 22-2 to Table 22-7 illustrate the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated. 22.3.1.1 Table 22-2. 27 26 25 32-bit Memory Data Bus Width SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Row[10:0] Row[10:0] Row[10:0] Row[10:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] M[1:0] M[1:0] M[1:0] M[1:0] Table 22-3. 27 26 25 SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Row[11:0] Row[11:0] Row[11:0] Row[11:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] M[1:0] M[1:0] M[1:0] M[1:0] Table 22-4. 27 26 25 SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Row[12:0] Row[12:0] Row[12:0] Row[12:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] M[1:0] M[1:0] M[1:0] M[1:0] Notes: 1. M[1:0] is the byte address inside a 32-bit word. 2. Bk[1] = BA1, Bk[0] = BA0. 202 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 22.3.1.2 Table 22-5. 27 26 25 16-bit Memory Data Bus Width SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Row[10:0] Row[10:0] Row[10:0] Row[10:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] M0 M0 M0 M0 Table 22-6. 27 26 25 SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Row[11:0] Row[11:0] Row[11:0] Row[11:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] M0 M0 M0 M0 Table 22-7. 27 26 25 SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Row[12:0] Row[12:0] Row[12:0] Row[12:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] M0 M0 M0 M0 Notes: 1. M0 is the byte address inside a 16-bit half-word. 2. Bk[1] = BA1, Bk[0] = BA0. 203 6384D-ATARM-04-May-09 22.4 22.4.1 Product Dependencies SDRAM Device Initialization The initialization sequence is generated by software. The SDRAM devices are initialized by the following sequence: 1. SDRAM features must be set in the configuration register: asynchronous timings (TRC, TRAS, etc.), number of columns, rows, CAS latency, and the data bus width. 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low Power Register. 3. The SDRAM memory type must be set in the Memory Device Register. 4. A minimum pause of 200 s is provided to precede any signal toggle. 5. (1) A NOP command is issued to the SDRAM devices. The application must set Mode to 1 in the Mode Register and perform a write access to any SDRAM address. 6. An All Banks Precharge command is issued to the SDRAM devices. The application must set Mode to 2 in the Mode Register and perform a write access to any SDRAM address. 7. Eight auto-refresh (CBR) cycles are provided. The application must set the Mode to 4 in the Mode Register and perform a write access to any SDRAM location eight times. 8. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM devices, in particular CAS latency and burst length. The application must set Mode to 3 in the Mode Register and perform a write access to the SDRAM. The write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000. 9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the SDRAM parameters (TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register and perform a write access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] are set to 1. For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM write access should be done at the address 0x20800000 or 0x20400000. 10. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and performing a write access at any location in the SDRAM. 11. Write the refresh rate into the count field in the SDRAMC Refresh Timer register. (Refresh rate = delay between refresh cycles). The SDRAM device requires a refresh every 15.625 s or 7.81 s. With a 100 MHz frequency, the Refresh Timer Counter Register must be set with the value 1562(15.652 s x 100 MHz) or 781(7.81 s x 100 MHz). After initialization, the SDRAM devices are fully functional. Note: 1. It is strongly recommended to respect the instructions stated in Step 5 of the initialization process in order to be certain that the subsequent commands issued by the SDRAMC will be taken into account. 204 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 22-1. SDRAM Device Initialization Sequence SDCKE tRP tRC tMRD SDCK SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE NBS Inputs Stable for 200 sec Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command 22.4.2 I/O Lines The pins used for interfacing the SDRAM Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAM Controller pins to their peripheral function. If I/O lines of the SDRAM Controller are not used by the application, they can be used for other purposes by the PIO Controller. 22.4.3 Interrupt The SDRAM Controller interrupt (Refresh Error notification) is connected to the Memory Controller. This interrupt may be ORed with other System Peripheral interrupt lines and is finally provided as the System Interrupt Source (Source 1) to the AIC (Advanced Interrupt Controller). Using the SDRAM Controller interrupt requires the AIC to be programmed first. 205 6384D-ATARM-04-May-09 22.5 22.5.1 Functional Description SDRAM Controller Write Cycle The SDRAM Controller allows burst access or single access. In both cases, the SDRAM controller keeps track of the active row in each bank, thus maximizing performance. To initiate a burst access, the SDRAM Controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out. If the next access is a write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the SDRAM Controller generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/write (tRCD) commands. For definition of these timing parameters, refer to the "SDRAMC Configuration Register" on page 216. This is described in Figure 22-2 below. Figure 22-2. Write Burst, 32-bit SDRAM Access tRCD = 3 SDCS SDCK SDRAMC_A[12:0] Row n col a col b col c col d col e col f col g col h col i col j col k col l RAS CAS SDWE D[31:0] Dna Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl 22.5.2 SDRAM Controller Read Cycle The SDRAM Controller allows burst access, incremental burst of unspecified length or single access. In all cases, the SDRAM Controller keeps track of the active row in each bank, thus maximizing performance of the SDRAM. If row and bank addresses do not match the previous row/bank address, then the SDRAM controller automatically generates a precharge command, activates the new row and starts the read command. To comply with the SDRAM timing parameters, additional clock cycles on SDCK are inserted between precharge and active commands (tRP) and between active and read command (tRCD). These two parameters are set in the configuration register of the SDRAM Controller. After a read command, additional wait states are generated to comply with the CAS latency (1, 2 or 3 clock delays specified in the configuration register). 206 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary For a single access or an incremented burst of unspecified length, the SDRAM Controller anticipates the next access. While the last value of the column is returned by the SDRAM Controller on the bus, the SDRAM Controller anticipates the read to the next column and thus anticipates the CAS latency. This reduces the effect of the CAS latency on the internal bus. For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads to the best performance. If the burst is broken (border, busy mode, etc.), the next access is handled as an incrementing burst of unspecified length. Figure 22-3. Read Burst, 32-bit SDRAM Access tRCD = 3 SDCS CAS = 2 SDCK SDRAMC_A[12:0] Row n col a col b col c col d col e col f RAS CAS SDWE D[31:0] (Input) Dna Dnb Dnc Dnd Dne Dnf 207 6384D-ATARM-04-May-09 22.5.3 Border Management When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAM controller generates a precharge command, activates the new row and initiates a read or write command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (tRP) command and the active/read (tRCD) command. This is described in Figure 22-4 below. Figure 22-4. Read Burst with Boundary Row Access TRP = 3 SDCS TRCD = 3 CAS = 2 SDCK Row n SDRAMC_A[12:0] col a col b col c col d Row m col a col b col c col d col e RAS CAS SDWE D[31:0] Dna Dnb Dnc Dnd Dma Dmb Dmc Dmd Dme 208 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 22.5.4 SDRAM Controller Refresh Cycles An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles between refresh cycles. A refresh error interrupt is generated when the previous auto-refresh command did not perform. It is acknowledged by reading the Interrupt Status Register (SDRAMC_ISR). When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the device is busy and the master is held by a wait signal. See Figure 22-5. Figure 22-5. Refresh Cycle Followed by a Read Access tRP = 3 SDCS tRC = 8 tRCD = 3 CAS = 2 SDCK Row n SDRAMC_A[12:0] col c col d Row m col a RAS CAS SDWE D[31:0] (input) Dnb Dnc Dnd Dma 22.5.5 Power Management Three low-power modes are available: * Self-refresh Mode: The SDRAM executes its own Auto-refresh cycle without control of the SDRAM Controller. Current drained by the SDRAM is very low. * Power-down Mode: Auto-refresh cycles are controlled by the SDRAM Controller. Between auto-refresh cycles, the SDRAM is in power-down. Current drained in Power-down mode is higher than in Self-refresh Mode. * Deep Power-down Mode: (Only available with Mobile SDRAM) The SDRAM contents are lost, but the SDRAM does not drain any current. The SDRAM Controller activates one low-power mode as soon as the SDRAM device is not selected. It is possible to delay the entry in self-refresh and power-down mode after the last access by programming a timeout value in the Low Power Register. 209 6384D-ATARM-04-May-09 22.5.5.1 Self-refresh Mode This mode is selected by programming the LPCB field to 1 in the SDRAMC Low Power Register. In self-refresh mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the SDRAM device become "don't care" except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAM Controller provides a sequence of commands and exits self-refresh mode. Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter or all banks of the SDRAM array. This feature reduces the self-refresh current. To configure this feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self Refresh (PASR) and Drive Strength (DS) parameters must be set in the Low Power Register and transmitted to the low-power SDRAM during initialization. The SDRAM device must remain in self-refresh mode for a minimum period of tRAS and may remain in self-refresh mode for an indefinite period. This is described in Figure 22-6. Figure 22-6. Self-refresh Mode Behavior Self Refresh Mode SRCB = 1 Write SDRAMC_SRR SDRAMC_A[12:0] Row TXSR = 3 SDCK SDCKE SDCS RAS CAS SDWE Access Request to the SDRAM Controller 210 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 22.5.5.2 Low-power Mode This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register. Power consumption is greater than in self-refresh mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low. In contrast to self-refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation). As no auto-refresh operations are performed by the SDRAM itself, the SDRAM Controller carries out the refresh operation. The exit procedure is faster than in self-refresh mode. This is described in Figure 22-7. Figure 22-7. Low-power Mode Behavior TRCD = 3 SDCS CAS = 2 Low Power Mode SDCK SDRAMC_A[12:0] Row n col a col b col c col d col e col f RAS CAS SDCKE D[31:0] (input) Dna Dnb Dnc Dnd Dne Dnf 211 6384D-ATARM-04-May-09 22.5.5.3 Deep Power-down Mode This mode is selected by programming the LPCB field to 3 in the SDRAMC Low Power Register. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost. When this mode is enabled, the application must not access to the SDRAM until a new initialization sequence is done (See "SDRAM Device Initialization" on page 204). This is described in Figure 22-8. Figure 22-8. Deep Power-down Mode Behavior tRP = 3 SDCS SDCK Row n SDRAMC_A[12:0] col c col d RAS CAS SDWE CKE D[31:0] (input) Dnb Dnc Dnd 212 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 22.6 SDRAM Controller (SDRAMC) User Interface Register Mapping Register SDRAMC Mode Register SDRAMC Refresh Timer Register SDRAMC Configuration Register SDRAMC Low Power Register SDRAMC Interrupt Enable Register SDRAMC Interrupt Disable Register SDRAMC Interrupt Mask Register SDRAMC Interrupt Status Register SDRAMC Memory Device Register Reserved Name SDRAMC_MR SDRAMC_TR SDRAMC_CR SDRAMC_LPR SDRAMC_IER SDRAMC_IDR SDRAMC_IMR SDRAMC_ISR SDRAMC_MDR - Access Read-write Read-write Read-write Read-write Write-only Write-only Read-only Read-only Read - Reset 0x00000000 0x00000000 0x852372C0 0x0 - - 0x0 0x0 0x0 - Table 22-8. Offset 0x00 0x04 0x08 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 - 0xFC 213 6384D-ATARM-04-May-09 22.6.1 SDRAMC Mode Register Register Name:SDRAMC_MR Access Type:Read-write Reset Value: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 25 - 17 - 9 - 1 MODE 24 - 16 - 8 - 0 * MODE: SDRAMC Command Mode This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed. MODE 0 0 0 0 0 0 1 1 0 1 0 1 Description Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. The SDRAM Controller issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. The SDRAM Controller issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. The SDRAM Controller issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most lowpower SDRAM devices use the bank 1. Deep power-down mode. Enters deep power-down mode. 1 0 0 1 0 1 1 1 0 214 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 22.6.2 SDRAMC Refresh Timer Register Register Name:SDRAMC_TR Access Type:Read-write Reset Value: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 COUNT 27 - 19 - 11 26 - 18 - 10 COUNT 3 2 1 0 25 - 17 - 9 24 - 16 - 8 * COUNT: SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The value to be loaded depends on the SDRAMC clock frequency (MCK: Master Clock), the refresh rate of the SDRAM device and the refresh burst length where 15.6 s per row is a typical value for a burst of length one. To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out. 215 6384D-ATARM-04-May-09 22.6.3 SDRAMC Configuration Register Register Name:SDRAMC_CR Access Type:Read-write Reset Value: 0x852372C0 31 30 TXSR 23 22 TRCD 15 14 TRC 7 DBW 6 CAS 5 4 NB 3 NR 2 13 12 11 10 TWR 1 NC 0 21 20 19 18 TRP 9 8 29 28 27 26 TRAS 17 16 25 24 * NC: Number of Column Bits Reset value is 8 column bits. NC 0 0 1 1 0 1 0 1 Column Bits 8 9 10 11 * NR: Number of Row Bits Reset value is 11 row bits. NR 0 0 1 1 0 1 0 1 Row Bits 11 12 13 Reserved * NB: Number of Banks Reset value is two banks. NB 0 1 Number of Banks 2 4 216 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * CAS: CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles are managed. CAS 0 0 1 1 0 1 0 1 CAS Latency (Cycles) Reserved 1 2 3 * DBW: Data Bus Width Reset value is 16 bits 0: Data bus width is 32 bits. 1: Data bus width is 16 bits. * TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15. * TRC: Row Cycle Delay Reset value is seven cycles. This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 0 and 15. * TRP: Row Precharge Delay Reset value is three cycles. This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles is between 0 and 15. * TRCD: Row to Column Delay Reset value is two cycles. This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of cycles is between 0 and 15. * TRAS: Active to Precharge Delay Reset value is five cycles. This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is between 0 and 15. * TXSR: Exit Self Refresh to Active Delay Reset value is eight cycles. This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles is between 0 and 15. 217 6384D-ATARM-04-May-09 22.6.4 SDRAMC Low Power Register Register Name:SDRAMC_LPR Access Type:Read-write Reset Value: 0x0 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 29 - 21 - 13 TIMEOUT 5 PASR 4 3 - 28 - 20 - 12 27 - 19 - 11 DS 2 - 1 LPCB 26 - 18 - 10 25 - 17 - 9 TCSR 0 24 - 16 - 8 * LPCB: Low-power Configuration Bits 00 Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCLK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to lowpower SDRAM. 01 10 11 * PASR: Partial Array Self-refresh (only for low-power SDRAM) PASR parameter is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of the SDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. This parameter must be set according to the SDRAM device specification. * TCSR: Temperature Compensated Self-Refresh (only for low-power SDRAM) TCSR parameter is transmitted to the SDRAM during initialization to set the refresh interval during self-refresh mode depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device specification. * DS: Drive Strength (only for low-power SDRAM) DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter must be set according to the SDRAM device specification. 218 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * TIMEOUT: Time to define when low-power mode is enabled 00 01 10 11 The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. Reserved. 219 6384D-ATARM-04-May-09 22.6.5 SDRAMC Interrupt Enable Register Register Name:SDRAMC_IER Access Type:Write-only 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 RES * RES: Refresh Error Status 0: No effect. 1: Enables the refresh error interrupt. 22.6.6 SDRAMC Interrupt Disable Register Register Name:SDRAMC_IDR Access Type:Write-only 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 RES * RES: Refresh Error Status 0: No effect. 1: Disables the refresh error interrupt. 220 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 22.6.7 SDRAMC Interrupt Mask Register Register Name:SDRAMC_IMR Access Type:Read-only 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 RES * RES: Refresh Error Status 0: The refresh error interrupt is disabled. 1: The refresh error interrupt is enabled. 22.6.8 SDRAMC Interrupt Status Register Register Name:SDRAMC_ISR Access Type:Read-only 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 RES * RES: Refresh Error Status 0: No refresh error has been detected since the register was last read. 1: A refresh error has been detected since the register was last read. 221 6384D-ATARM-04-May-09 22.6.9 SDRAMC Memory Device Register Register Name:SDRAMC_MDR Access Type:Read-write 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 MD 24 - 16 - 8 - 0 * MD: Memory Device Type 00 01 10 11 SDRAM Low-power SDRAM Reserved Reserved. 222 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23. Error Corrected Code Controller (ECC) 23.1 Overview NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur which can be detected/corrected by ECC code. The ECC Controller is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors in data. The ECC controller is capable of single bit error correction and 2-bit random detection. When NAND Flash/SmartMedia have more than 2 bits of errors, the data cannot be corrected. The ECC user interface is compliant with the ARM(R) Advanced Peripheral Bus (APB rev2). 23.2 Block Diagram Figure 23-1. Block Diagram Static Memory Controller NAND Flash SmartMedia Logic ECC Controller Ctrl/ECC Algorithm User Interface APB 223 6384D-ATARM-04-May-09 23.3 Functional Description A page in NAND Flash and SmartMedia memories contains an area for main data and an additional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page size corresponds to the number of words in the main area plus the number of words in the extra area used for redundancy. Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, NAND Flash providers recommend to utilize either 1 ECC per 256 bytes of data, 1 ECC per 512 bytes of data or 1 ECC for all of the page. The only configurations required for ECC are the NAND Flash or the SmartMedia page size (528/2112/4224) and the type of correction wanted (1 ECC for all the page/1 ECC per 256 bytes of data /1 ECC per 512 bytes of data). Page size is configured setting the PAGESIZE field in the ECC Mode Register (ECC_MR). Type of correction is configured setting the TYPCORRECT field in the ECC Mode Register (ECC_MR). ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND Flash or the SmartMedia is detected. Read and write access must start at a page boundary. ECC results are available as soon as the counter reaches the end of the main area. Values in the ECC Parity Registers (ECC_PR0 to ECC_PR15) are then valid and locked until a new start condition occurs (read/write command followed by address cycles). 23.3.1 Write Access Once the Flash memory page is written, the computed ECC codes are available in the ECC Parity (ECC_PR0 to ECC_PR15) registers. The ECC code values must be written by the software application in the extra area used for redundancy. The number of write accesses in the extra area is a function of the value of the type of correction field. For example, for 1 ECC per 256 bytes of data for a page of 512 bytes, only the values of ECC_PR0 and ECC_PR1 must be written by the software application. Other registers are meaningless. 23.3.2 Read Access After reading the whole data in the main area, the application must perform read accesses to the extra area where ECC code has been previously stored. Error detection is automatically performed by the ECC controller. Please note that it is mandatory to read consecutively the entire main area and the locations where Parity and NParity values have been previously stored to let the ECC controller perform error detection. The application can check the ECC Status Registers (ECC_SR1/ECC_SR2) for any detected errors. It is up to the application to correct any detected error. ECC computation can detect four different circumstances: * No error: XOR between the ECC computation and the ECC code stored at the end of the NAND Flash or SmartMedia page is equal to 0. No error flags in the ECC Status Registers (ECC_SR1/ECC_SR2). * Recoverable error: Only the RECERR flags in the ECC Status registers (ECC_SR1/ECC_SR2) are set. The corrupted word offset in the read page is defined by the WORDADDR field in the ECC Parity Registers (ECC_PR0 to ECC_PR15). The corrupted bit position in the concerned word is defined in the BITADDR field in the ECC Parity Registers (ECC_PR0 to ECC_PR15). 224 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * ECC error: The ECCERR flag in the ECC Status Registers (ECC_SR1/ECC_SR2) are set. An error has been detected in the ECC code stored in the Flash memory. The position of the corrupted bit can be found by the application performing an XOR between the Parity and the NParity contained in the ECC code stored in the Flash memory. * Non correctable error: The MULERR flag in the ECC Status Registers (ECC_SR1/ECC_SR2) are set. Several unrecoverable errors have been detected in the Flash memory page. ECC Status Registers, ECC Parity Registers are cleared when a read/write command is detected or a software reset is performed. For Single-bit Error Correction and Double-bit Error Detection (SEC-DED) hsiao code is used. 24-bit ECC is generated in order to perform one bit correction per 256 or 512 bytes for pages of 512/2048/4096 8-bit words. 32-bit ECC is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-bit words.They are generated according to the schemes shown in Figure 23-2 and Figure 23-3. Figure 23-2. Parity Generation for 512/1024/2048/4096 8-bit Words 1st byte 2nd byte 3rd byte 4 th byte Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 P8 P8' P8 P8' P16 P32 P16' PX (page size -3 )th byte (page size -2 )th byte (page size -1 )th byte Page size th byte Bit7 Bit7 Bit7 Bit7 P1 P2 Bit6 Bit6 Bit6 Bit6 P1' Bit5 Bit5 Bit5 Bit5 P1 Bit4 Bit4 Bit4 Bit4 P1' P2' Bit3 Bit3 Bit3 Bit3 P1 P2 Bit2 Bit2 Bit2 Bit2 P1' Bit1 Bit1 Bit1 Bit1 P1 P2' P4' Bit0 Bit0 Bit0 Bit0 P1' P8 P8' P8 P8' P16 P32 P16' PX' P4 Page size Page size Page size Page size = 512 = 1024 = 2048 = 4096 Px = 2048 Px = 4096 Px = 8192 Px = 16384 P1=bit7(+)bit5(+)bit3(+)bit1(+)P1 P2=bit7(+)bit6(+)bit3(+)bit2(+)P2 P4=bit7(+)bit6(+)bit5(+)bit4(+)P4 P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1' P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2' P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4' To calculate P8' to PX' and P8 to PX, apply the algorithm that follows. Page size = 2n for i =0 to n 225 6384D-ATARM-04-May-09 begin for (j = 0 to page_size_byte) begin if(j[i] ==1) P[2i+3]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3] else P[2i+3]'=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3]' end end 226 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 6384D-ATARM-04-May-09 1st word 2nd word 3rd word 4th word Figure 23-3. Parity Generation for 512/1024/2048/4096 16-bit Words (Page size -3 )th word (Page size -2 )th word (Page size -1 )th word Page size th word (+) AT91SAM9G20 Preliminary 227 To calculate P8' to PX' and P8 to PX, apply the algorithm that follows. Page size = 2n for i =0 to n begin for (j = 0 to page_size_word) begin if(j[i] ==1) P[2i+3]= bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2n+3] else P[2i+3]'=bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3]' end end 228 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.4 Error Corrected Code Controller (ECC) User Interface Register Mapping Register Name ECC_CTRL ECC_MD ECC_SR1 ECC_PR0 ECC_PR1 ECC_SR2 ECC_PR2 ECC_PR3 ECC_PR4 ECC_PR5 ECC_PR6 ECC_PR7 ECC_PR8 ECC_PR9 ECC_PR10 ECC_PR11 ECC_PR12 ECC_PR13 ECC_PR14 ECC_PR15 - Access Write-only Read-write Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only - Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - Table 23-1. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x14 - 0xFC ECC Control Register ECC Mode Register ECC Status1 Register ECC Parity Register 0 ECC Parity Register 1 ECC Status2 Register ECC Parity 2 ECC Parity 3 ECC Parity 4 ECC Parity 5 ECC Parity 6 ECC Parity 7 ECC Parity 8 ECC Parity 9 ECC Parity 10 ECC Parity 11 ECC Parity 12 ECC Parity 13 ECC Parity 14 ECC Parity 15 Reserved 229 6384D-ATARM-04-May-09 23.4.1 Name: ECC Control Register ECC_CR Access Type:Write-only 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 RST * RST: RESET Parity Provides reset to current ECC by software. 1: Reset ECC Parity registers 0: No effect 230 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.4.2 ECC Mode Register Register Name:ECC_MR Access Type:Read-write 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 TYPCORREC 28 - 20 - 12 - 4 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 PAGESIZE 24 - 16 - 8 - 0 * PAGESIZE: Page Size This field defines the page size of the NAND Flash device. Page Size 00 01 10 11 Description 528 words 1056 words 2112 words 4224 words A word has a value of 8 bits or 16 bits, depending on the NAND Flash or SmartMedia memory organization. * TYPECORREC: Type of Correction 00: 1 bit correction for a page size of 512/1024/2048/4096 bytes. 01: 1 bit correction for 256 bytes of data for a page size of 512/2048/4096 bytes. 10: 1 bit correction for 512 bytes of data for a page size of 512/2048/4096 bytes. 231 6384D-ATARM-04-May-09 23.4.3 ECC Status Register 1 Register Name:ECC_SR1 Access Type:Read-only 31 - 23 - 15 - 7 - 30 ECCERR7 22 ECCERR5 14 MULERR3 6 MULERR1 29 ECCERR7 21 ECCERR5 13 ECCERR3 5 ECCERR1 28 RECERR7 20 RECERR5 12 RECERR3 4 RECERR1 27 - 19 - 11 - 3 - 26 ECCERR6 18 ECCERR4 10 MULERR2 2 ECCERR0 25 ECCERR6 17 ECCERR4 9 ECCERR2 1 ECCERR0 24 RECERR6 16 RECERR4 8 RECERR2 0 RECERR0 * RECERR0: Recoverable Error 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. * ECCERR0: ECC Error 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. If TYPECORRECT = 0, read both ECC Parity 0 and ECC Parity 1 registers, the error occurred at the location which contains a 1 in the least significant 16 bits; else read ECC Parity 0 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR0: Multiple Error 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR1: Recoverable Error in the page between the 256th and the 511th bytes or the 512th and the 1023rd bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. * ECCERR1: ECC Error in the page between the 256th and the 511th bytes or the 512th and the 1023rd bytes Fixed to 0 if TYPECORREC = 0 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 1 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR1: Multiple Error in the page between the 256th and the 511th bytes or the 512th and the 1023rd bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 232 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 1 = Multiple Errors Detected. * RECERR2: Recoverable Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected. * ECCERR2: ECC Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 2 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR2: Multiple Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR3: Recoverable Error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. * ECCERR3: ECC Error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 3 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR3: Multiple Error in the page between the 768th and the 1023rd bytes or the 1536th and the 2047th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR4: Recoverable Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 233 6384D-ATARM-04-May-09 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. * ECCERR4: ECC Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 4 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR4: Multiple Error in the page between the 1024th and the 1279th bytes or the 2048th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR5: Recoverable Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected * ECCERR5: ECC Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 5 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR5: Multiple Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR6: Recoverable Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. * ECCERR6: ECC Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 234 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 6 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR6: Multiple Error in the page between the 1536th and the 1791st bytes or the 3072nd and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR7: Recoverable Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected. * ECCERR7: ECC Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 7 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR7: Multiple Error in the page between the 1792nd and the 2047th bytes or the 3584th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. 235 6384D-ATARM-04-May-09 23.4.4 ECC Status Register 2 Register Name:ECC_SR2 Access Type:Read-only 31 - 23 - 15 - 7 - 30 ECCERR15 22 ECCERR13 14 MULERR11 6 MULERR9 29 ECCERR15 21 ECCERR13 13 ECCERR11 5 ECCERR9 28 RECERR15 20 RECERR13 12 RECERR11 4 RECERR9 27 - 19 - 11 - 3 - 26 ECCERR14 18 ECCERR12 10 MULERR10 2 ECCERR8 25 ECCERR14 17 ECCERR12 9 ECCERR10 1 ECCERR8 24 -RECERR14 16 RECERR12 8 RECERR10 0 RECERR8 * RECERR8: Recoverable Error in the page between the 2048th and the 2303rd bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected * ECCERR8: ECC Error in the page between the 2048th and the 2303rd bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 8 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR8: Multiple Error in the page between the 2048th and the 2303rd bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR9: Recoverable Error in the page between the 2304th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. * ECCERR9: ECC Error in the page between the 2304th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 9 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR9: Multiple Error in the page between the 2304th and the 2559th bytes Fixed to 0 if TYPECORREC = 0. 236 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR10: Recoverable Error in the page between the 2560th and the 2815th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected. * ECCERR10: ECC Error in the page between the 2560th and the 2815th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 10 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR10: Multiple Error in the page between the 2560th and the 2815th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR11: Recoverable Error in the page between the 2816th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected.. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected * ECCERR11: ECC Error in the page between the 2816th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 11 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR11: Multiple Error in the page between the 2816th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR12: Recoverable Error in the page between the 3072nd and the 3327th bytes Fixed to 0 if TYPECORREC = 0 0 = No Errors Detected 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected 237 6384D-ATARM-04-May-09 * ECCERR12: ECC Error in the page between the 3072nd and the 3327th bytes Fixed to 0 if TYPECORREC = 0 0 = No Errors Detected 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 12 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR12: Multiple Error in the page between the 3072nd and the 3327th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR13: Recoverable Error in the page between the 3328th and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected. * ECCERR13: ECC Error in the page between the 3328th and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 13 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR13: Multiple Error in the page between the 3328th and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR14: Recoverable Error in the page between the 3584th and the 3839th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected. * ECCERR14: ECC Error in the page between the 3584th and the 3839th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 14 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR14: Multiple Error in the page between the 3584th and the 3839th bytes Fixed to 0 if TYPECORREC = 0. 238 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. * RECERR15: Recoverable Error in the page between the 3840th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Errors Detected. 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise, multiple uncorrected errors were detected * ECCERR15: ECC Error in the page between the 3840th and the 4095th bytes Fixed to 0 if TYPECORREC = 0 0 = No Errors Detected. 1 = A single bit error occurred in the ECC bytes. Read ECC Parity 15 register, the error occurred at the location which contains a 1 in the least significant 24 bits. * MULERR15: Multiple Error in the page between the 3840th and the 4095th bytes Fixed to 0 if TYPECORREC = 0. 0 = No Multiple Errors Detected. 1 = Multiple Errors Detected. 239 6384D-ATARM-04-May-09 23.5 Registers for 1 ECC for a page of 512/1024/2048/4096 bytes 23.5.1 ECC Parity Register 0 Register Name:ECC_PR0 Access Type:Read-only 31 - 23 - 15 7 30 - 22 - 14 6 WORDADDR 29 - 21 - 13 5 28 - 20 - 12 WORDADDR 4 3 2 BITADDR 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR: Bit Address During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR: Word Address During a page read, this value contains the word address (8-bit or 16-bit word depending on the memory plane organization) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. 240 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.5.2 ECC Parity Register 1 Register Name:ECC_PR1 Access Type:Read-only 31 - 23 - 15 7 30 - 22 - 14 6 29 - 21 - 13 5 28 - 20 - 12 NPARITY 4 NPARITY 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 * NPARITY: Parity N 241 6384D-ATARM-04-May-09 23.6 Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word 23.6.1 ECC Parity Register 0 Register Name:ECC_PR0 Access Type:Read-only 31 23 15 7 30 22 14 NPARITY0 6 5 WORDADDR0 4 3 2 29 21 13 28 20 NPARITY0 12 27 19 11 26 18 10 WORDADD0 1 BITADDR0 0 25 17 9 24 16 8 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR0: corrupted Bit Address in the page between the first byte and the 511th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR0: corrupted Word Address in the page between the first byte and the 511th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY0: Parity N 242 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.6.2 ECC Parity Register 1 Register Name:ECC_PR1 Access Type:Read-only 31 23 15 7 30 22 14 NPARITY1 6 5 WORDADDR1 4 3 2 29 21 13 28 20 NPARITY1 12 27 19 11 26 18 10 WORDADD1 1 BITADDR1 0 25 17 9 24 16 8 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR1: corrupted Bit Address in the page between the 512th and the 1023rd bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR1: corrupted Word Address in the page between the 512th and the 1023rd bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY1: Parity N 243 6384D-ATARM-04-May-09 23.6.3 ECC Parity Register 2 Register Name:ECC_PR2 Access Type:Read-only 31 23 15 7 30 22 14 NPARITY2 6 5 WORDADDR2 4 3 2 29 21 13 28 20 NPARITY2 12 27 19 11 26 18 10 WORDADD2 1 BITADDR2 0 25 17 9 24 16 8 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR2: corrupted Bit Address in the page between the 1023rd and the 1535th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR2: corrupted Word Address in the page in the page between the 1023rd and the 1535th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY2: Parity N 244 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.6.4 ECC Parity Register 3 Register Name:ECC_PR3 Access Type:Read-only 31 23 15 7 30 22 14 NPARITY3 6 5 WORDADDR3 4 3 2 29 21 13 28 20 NPARITY3 12 27 19 11 26 18 10 WORDADD3 1 BITADDR3 0 25 17 9 24 16 8 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR3: corrupted Bit Address in the page between the1536th and the 2047th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR3 corrupted Word Address in the page between the 1536th and the 2047th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY3 Parity N 245 6384D-ATARM-04-May-09 23.6.5 ECC Parity Register 4 Register Name:ECC_PR4 Access Type:Read-only 31 23 15 7 30 22 14 NPARITY4 6 5 WORDADDR4 4 3 2 29 21 13 28 20 NPARITY4 12 27 19 11 26 18 10 WORDADD4 1 BITADDR4 0 25 17 9 24 16 8 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR4: corrupted Bit Address in the page between the 2048th and the 2559th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR4: corrupted Word Address in the page between the 2048th and the 2559th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY4: Parity N 246 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.6.6 ECC Parity Register 5 Register Name:ECC_PR5 Access Type:Read-only 31 23 15 7 30 22 14 NPARITY5 6 5 WORDADDR5 4 3 2 29 21 13 28 20 NPARITY5 12 27 19 11 26 18 10 WORDADD5 1 BITADDR5 0 25 17 9 24 16 8 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR5: corrupted Bit Address in the page between the 2560th and the 3071st bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR5: corrupted Word Address in the page between the 2560th and the 3071st bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY5: Parity N 247 6384D-ATARM-04-May-09 23.6.7 ECC Parity Register 6 Register Name:ECC_PR6 Access Type:Read-only 31 23 15 7 30 22 14 NPARITY6 6 5 WORDADDR6 4 3 2 29 21 13 28 20 NPARITY6 12 27 19 11 26 18 10 WORDADD6 1 BITADDR6 0 25 17 9 24 16 8 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR6: corrupted Bit Address in the page between the 3072nd and the 3583rd bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR6: corrupted Word Address in the page between the 3072nd and the 3583rd bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY6: Parity N 248 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.6.8 ECC Parity Register 7 Register Name:ECC_PR7 Access Type:Read-only 31 23 15 7 30 22 14 NPARITY7 6 5 WORDADDR7 4 3 2 29 21 13 28 20 NPARITY7 12 27 19 11 26 18 10 WORDADD7 1 BITADDR7 0 25 17 9 24 16 8 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR7: corrupted Bit Address in the page between the 3584h and the 4095th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR7: corrupted Word Address in the page between the 3584th and the 4095th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY7: Parity N 249 6384D-ATARM-04-May-09 23.7 Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word 23.7.1 ECC Parity Register 0 Register Name:ECC_PR0 Access Type:Read-only 31 23 0 15 7 30 22 14 NPARITY0 6 5 WORDADDR0 4 29 21 13 28 20 12 27 19 NPARITY0 11 0 3 26 18 10 2 25 17 9 WORDADD0 1 BITADDR0 24 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR0: corrupted Bit Address in the page between the first byte and the 255th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR0: corrupted Word Address in the page between the first byte and the 255th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY0: Parity N 250 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.7.2 ECC Parity Register 1 Register Name:ECC_PR1 Access Type:Read-only 31 23 0 15 7 30 22 14 NPARITY1 6 5 WORDADDR1 4 29 21 13 28 20 12 27 19 NPARITY1 11 0 3 26 18 10 2 25 17 9 WORDADD1 1 BITADDR1 24 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area * BITADDR1: corrupted Bit Address in the page between the 256th and the 511th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR1: corrupted Word Address in the page between the 256th and the 511th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY1: Parity N 251 6384D-ATARM-04-May-09 23.7.3 ECC Parity Register 2 Register Name:ECC_PR2 Access Type:Read-only 31 23 0 15 7 30 22 14 NPARITY2 6 5 WORDADDR2 4 29 21 13 28 20 12 27 19 NPARITY2 11 0 3 26 18 10 2 25 17 9 WORDADD2 1 BITADDR2 24 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR2: corrupted Bit Address in the page between the 512th and the 767th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR2: corrupted Word Address in the page between the 512th and the 767th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY2: Parity N 252 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.7.4 ECC Parity Register 3 Register Name:ECC_PR3 Access Type:Read-only 31 23 0 15 7 30 22 14 NPARITY3 6 5 WORDADDR3 4 29 21 13 28 20 12 27 19 NPARITY3 11 0 3 26 18 10 2 25 17 9 WORDADD3 1 BITADDR3 24 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR3: corrupted Bit Address in the page between the 768th and the 1023rd bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR3: corrupted Word Address in the page between the 768th and the 1023rd bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless * NPARITY3: Parity N 253 6384D-ATARM-04-May-09 23.7.5 ECC Parity Register 4 Register Name:ECC_PR4 Access Type:Read-only 31 23 0 15 7 30 22 14 NPARITY4 6 5 WORDADDR4 4 29 21 13 28 20 12 27 19 NPARITY4 11 0 3 26 18 10 2 25 17 9 WORDADD4 1 BITADDR4 24 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area * BITADDR4: corrupted bit address in the page between the 1024th and the 1279th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR4: corrupted word address in the page between the 1024th and the 1279th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY4 Parity N 254 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.7.6 ECC Parity Register 5 Register Name:ECC_PR5 Access Type:Read-only 31 23 0 15 7 30 22 14 NPARITY5 6 5 WORDADDR5 4 29 21 13 28 20 12 27 19 NPARITY5 11 0 3 26 18 10 2 25 17 9 WORDADD5 1 BITADDR5 24 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR5: corrupted Bit Address in the page between the 1280th and the 1535th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR5: corrupted Word Address in the page between the 1280th and the 1535th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY5: Parity N 255 6384D-ATARM-04-May-09 23.7.7 ECC Parity Register 6 Register Name:ECC_PR6 Access Type:Read-only 31 23 0 15 7 30 22 14 NPARITY6 6 5 WORDADDR6 4 29 21 13 28 20 12 27 19 NPARITY6 11 0 3 26 18 10 2 25 17 9 WORDADDR6 1 BITADDR6 24 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR6: corrupted bit address in the page between the 1536th and the 1791st bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR6: corrupted word address in the page between the 1536th and the 1791st bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY6: Parity N 256 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.7.8 ECC Parity Register 7 Register Name:ECC_PR7 Access Type:Read-only 31 23 0 15 7 30 22 14 NPARITY7 6 5 WORDADDR7 4 29 21 13 28 20 12 27 19 NPARITY7 11 0 3 26 18 10 2 25 17 9 WORDADDR7 1 BITADDR7 24 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR7: corrupted Bit Address in the page between the 1792nd and the 2047th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR7: corrupted Word Address in the page between the 1792nd and the 2047th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY7: Parity N 257 6384D-ATARM-04-May-09 23.7.9 ECC Parity Register 8 Register Name:ECC_PR8 Access Type:Read-only 31 23 0 15 7 30 22 14 NPARITY8 6 5 WORDADDR8 4 29 21 13 28 20 12 27 19 NPARITY8 11 0 3 26 18 10 2 25 17 9 WORDADDR8 1 BITADDR8 24 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR8: corrupted Bit Address in the page between the 2048th and the2303rd bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR8: corrupted Word Address in the page between the 2048th and the 2303rd bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY8: Parity N. 258 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.7.10 ECC Parity Register 9 Register Name:ECC_PR9 Access Type:Read-only 31 23 0 15 7 30 22 14 NPARITY9 6 5 WORDADDR9 4 29 21 13 28 20 12 27 19 NPARITY9 11 0 3 26 18 10 2 25 17 9 WORDADDR9 1 BITADDR9 24 16 8 0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area * BITADDR9: corrupted bit address in the page between the 2304th and the 2559th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR9: corrupted word address in the page between the 2304th and the 2559th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless * NPARITY9 Parity N 259 6384D-ATARM-04-May-09 23.7.11 ECC Parity Register 10 Register Name:ECC_PR10 Access Type:Read-only 31 23 0 15 7 30 22 29 21 28 20 12 4 27 19 NPARITY10 11 0 3 26 18 10 2 25 17 9 WORDADDR10 1 BITADDR10 24 16 8 0 14 13 NPARITY10 6 5 WORDADDR10 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR10: corrupted Bit Address in the page between the 2560th and the 2815th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR10: corrupted Word Address in the page between the 2560th and the 2815th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY10: Parity N 260 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.7.12 ECC Parity Register 11 Register Name:ECC_PR11 Access Type:Read-only 31 23 0 15 7 30 22 29 21 28 20 12 4 27 19 NPARITY11 11 0 3 26 18 10 2 25 17 9 WORDADDR11 1 BITADDR11 24 16 8 0 14 13 NPARITY11 6 5 WORDADDR11 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR11: corrupted Bit Address in the page between the 2816th and the 3071st bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR11: corrupted Word Address in the page between the 2816th and the 3071st bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY11: Parity N 261 6384D-ATARM-04-May-09 23.7.13 ECC Parity Register 12 Register Name:ECC_PR12 Access Type:Read-only 31 23 0 15 7 30 22 29 21 28 20 12 4 27 19 NPARITY12 11 0 3 26 18 10 2 25 17 9 WORDADDR12 1 BITADDR12 24 16 8 0 14 13 NPARITY12 6 5 WORDADDR12 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR12; corrupted Bit Address in the page between the 3072nd and the 3327th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR12: corrupted Word Address in the page between the 3072nd and the 3327th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY12: Parity N 262 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.7.14 ECC Parity Register 13 Register Name:ECC_PR13 Access Type:Read-only 31 23 0 15 7 30 22 29 21 28 20 12 4 27 19 NPARITY13 11 0 3 26 18 10 2 25 17 9 WORDADDR13 1 BITADDR13 24 16 8 0 14 13 NPARITY13 6 5 WORDADDR13 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR13: corrupted Bit Address in the page between the 3328th and the 3583rd bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR13: corrupted Word Address in the page between the 3328th and the 3583rd bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY13: Parity N 263 6384D-ATARM-04-May-09 23.7.15 ECC Parity Register 14 Register Name:ECC_PR14 Access Type:Read-only 31 23 0 15 7 30 22 29 21 28 20 12 4 27 19 NPARITY14 11 0 3 26 18 10 2 25 17 9 WORDADDR14 1 BITADDR14 24 16 8 0 14 13 NPARITY14 6 5 WORDADDR14 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area. * BITADDR14: corrupted Bit Address in the page between the 3584th and the 3839th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR14: corrupted Word Address in the page between the 3584th and the 3839th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY14: Parity N 264 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23.7.16 ECC Parity Register 15 Register Name:ECC_PR15 Access Type:Read-only 31 23 0 15 7 30 22 29 21 28 20 12 4 27 19 NPARITY15 11 0 3 26 18 10 2 25 17 9 WORDADDR15 1 BITADDR15 24 16 8 0 14 13 NPARITY15 6 5 WORDADDR15 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area * BITADDR15: corrupted Bit Address in the page between the 3840th and the 4095th bytes During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR15: corrupted Word Address in the page between the 3840th and the 4095th bytes During a page read, this value contains the word address (8-bit word) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * NPARITY15 Parity N 265 6384D-ATARM-04-May-09 266 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 24. Peripheral DMA Controller (PDC) 24.1 Overview The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by the AHB to ABP bridge. The PDC contains 24 channels. The full-duplex peripherals feature 21 mono directional channels used in pairs (transmit only or receive only). The half-duplex peripherals feature 1 bidirectional channel. The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The user interface of mono directional channels (receive only or transmit only), contains two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current transfer and one set (pointer, counter) for next transfer. The bi-directional channel user interface contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is used by current transmit, next transmit, current receive and next receive. Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly reduces the number of clock cycles required for a data transfer, which improves microcontroller performance. To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself. 267 6384D-ATARM-04-May-09 24.2 Block Diagram Figure 24-1. Block Diagram FULL DUPLEX PERIPHERAL THR PDC Channel A PDC RHR PDC Channel B Control Status & Control HALF DUPLEX PERIPHERAL THR PDC Channel C RHR Control Control Status & Control RECEIVE or TRANSMIT PERIPHERAL RHR or THR PDC Channel D Control Status & Control 24.3 24.3.1 Functional Description Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR). However, the transmit and receive parts of each type are programmed differently: the 268 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary transmit and receive parts of a full duplex peripheral can be programmed at the same time, whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a time. 32-bit pointers define the access location in memory for current and next transfer, whether it is for read (transmit) or write (receive). 16-bit counters define the size of current and next transfers. It is possible, at any moment, to read the number of transfers left for each channel. The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status for each channel is located in the associated peripheral status register. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in the peripheral's Transfer Control Register. At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These flags are visible in the peripheral status register (ENDRX, ENDTX, RXBUFF, and TXBUFE). Refer to Section 24.3.3 and to the associated peripheral user interface. 24.3.2 Memory Pointers Each full duplex peripheral is connected to the PDC by a receive channel and a transmit channel. Both channels have 32-bit memory pointers that point respectively to a receive area and to a transmit area in on- and/or off-chip memory. Each half duplex peripheral is connected to the PDC by a bidirectional channel. This channel has two 32-bit memory pointers, one for current transfer and the other for next transfer. These pointers point to transmit or receive data depending on the operating mode of the peripheral. Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented respectively by 1, 2 or 4 bytes. If a memory pointer address changes in the middle of a transfer, the PDC channel continues operating using the new address. 24.3.3 Transfer Counters Each channel has two 16-bit counters, one for current transfer and the other one for next transfer. These counters define the size of data to be transferred by the channel. The current transfer counter is decremented first as the data addressed by current memory pointer starts to be transferred. When the current transfer counter reaches zero, the channel checks its next transfer counter. If the value of next counter is zero, the channel stops transferring data and sets the appropriate flag. But if the next counter value is greater then zero, the values of the next pointer/next counter are copied into the current pointer/current counter and the channel resumes the transfer whereas next pointer/next counter get zero/zero as values. At the end of this transfer the PDC channel sets the appropriate flags in the Peripheral Status Register. The following list gives an overview of how status register flags behave depending on the counters' values: * ENDRX flag is set when the PERIPH_RCR register reaches zero. * RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero. * ENDTX flag is set when the PERIPH_TCR register reaches zero. * TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero. These status flags are described in the Peripheral Status Register. 269 6384D-ATARM-04-May-09 24.3.4 Data Transfers The serial peripheral triggers its associated PDC channels' transfers using transmit enable (TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the peripheral's user interface. When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which then requests access to the Matrix. When access is granted, the PDC receive channel starts reading the peripheral Receive Holding Register (RHR). The read data are stored in an internal buffer and then written to memory. When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit channel which then requests access to the Matrix. When access is granted, the PDC transmit channel reads data from memory and puts them to Transmit Holding Register (THR) of its associated peripheral. The same peripheral sends data according to its mechanism. 24.3.5 PDC Flags and Peripheral Status Register Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC sends back flags to the peripheral. All these flags are only visible in the Peripheral Status Register. Depending on the type of peripheral, half or full duplex, the flags belong to either one single channel or two different channels. 24.3.5.1 Receive Transfer End This flag is set when PERIPH_RCR register reaches zero and the last data has been transferred to memory. It is reset by writing a non zero value in PERIPH_RCR or PERIPH_RNCR. 24.3.5.2 Transmit Transfer End This flag is set when PERIPH_TCR register reaches zero and the last data has been written into peripheral THR. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR. 24.3.5.3 Receive Buffer Full This flag is set when PERIPH_RCR register reaches zero with PERIPH_RNCR also set to zero and the last data has been transferred to memory. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR. 24.3.5.4 Transmit Buffer Empty This flag is set when PERIPH_TCR register reaches zero with PERIPH_TNCR also set to zero and the last data has been written into peripheral THR. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR. 270 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 24.4 Peripheral DMA Controller (PDC) User Interface Register Mapping Register Receive Pointer Register Receive Counter Register Transmit Pointer Register Transmit Counter Register Receive Next Pointer Register Receive Next Counter Register Transmit Next Pointer Register Transmit Next Counter Register Transfer Control Register Transfer Status Register Name PERIPH _RPR PERIPH_RCR PERIPH_TPR PERIPH_TCR PERIPH_RNPR PERIPH_RNCR PERIPH_TNPR PERIPH_TNCR PERIPH_PTCR PERIPH_PTSR (1) Table 24-1. Offset 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 Note: Access Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Write-only Read-only Reset 0 0 0 0 0 0 0 0 0 0 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI, etc.) 271 6384D-ATARM-04-May-09 24.4.1 Receive Pointer Register Register Name: PERIPH_RPR Access Type: 31 Read-write 30 29 28 RXPTR 27 26 25 24 23 22 21 20 RXPTR 19 18 17 16 15 14 13 12 RXPTR 11 10 9 8 7 6 5 4 RXPTR 3 2 1 0 * RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR. 272 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 24.4.2 Receive Counter Register Register Name: PERIPH_RCR Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RXCTR 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 RXCTR 3 2 1 0 * RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0 = Stops peripheral data transfer to the receiver 1 - 65535 = Starts peripheral data transfer if corresponding channel is active 273 6384D-ATARM-04-May-09 24.4.3 Transmit Pointer Register Register Name: PERIPH_TPR Access Type: 31 Read-write 30 29 28 TXPTR 27 26 25 24 23 22 21 20 TXPTR 19 18 17 16 15 14 13 12 TXPTR 11 10 9 8 7 6 5 4 TXPTR 3 2 1 0 * TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR. 24.4.4 Transmit Counter Register Register Name: PERIPH_TCR Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 TXCTR 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 TXCTR 3 2 1 0 * TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0 = Stops peripheral data transfer to the transmitter 1- 65535 = Starts peripheral data transfer if corresponding channel is active 274 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 24.4.5 Receive Next Pointer Register Register Name: PERIPH_RNPR Access Type: 31 Read-write 30 29 28 RXNPTR 27 26 25 24 23 22 21 20 RXNPTR 19 18 17 16 15 14 13 12 RXNPTR 11 10 9 8 7 6 5 4 RXNPTR 3 2 1 0 * RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. 275 6384D-ATARM-04-May-09 24.4.6 Receive Next Counter Register Register Name: PERIPH_RNCR Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RXNCTR 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 RXNCTR 3 2 1 0 * RXNCTR: Receive Next Counter RXNCTR contains next receive buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR. 276 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 24.4.7 Transmit Next Pointer Register Register Name: PERIPH_TNPR Access Type: 31 Read-write 30 29 28 TXNPTR 27 26 25 24 23 22 21 20 TXNPTR 19 18 17 16 15 14 13 12 TXNPTR 11 10 9 8 7 6 5 4 TXNPTR 3 2 1 0 * TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. 277 6384D-ATARM-04-May-09 24.4.8 Transmit Next Counter Register Register Name: PERIPH_TNCR Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 TXNCTR 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 TXNCTR 3 2 1 0 * TXNCTR: Transmit Counter Next TXNCTR contains next transmit buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR. 278 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 24.4.9 Transfer Control Register Register Name: PERIPH_PTCR Access Type: 31 - 23 - 15 - 7 - Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 TXTDIS 1 RXTDIS 24 - 16 - 8 TXTEN 0 RXTEN * RXTEN: Receiver Transfer Enable 0 = No effect. 1 = Enables PDC receiver channel requests if RXTDIS is not set. When a half duplex peripheral is connected to the PDC, enabling the receiver channel requests automatically disables the transmitter channel requests. It is forbidden to set both TXTEN and RXTEN for a half duplex peripheral. * RXTDIS: Receiver Transfer Disable 0 = No effect. 1 = Disables the PDC receiver channel requests. When a half duplex peripheral is connected to the PDC, disabling the receiver channel requests also disables the transmitter channel requests. * TXTEN: Transmitter Transfer Enable 0 = No effect. 1 = Enables the PDC transmitter channel requests. When a half duplex peripheral is connected to the PDC, it enables the transmitter channel requests only if RXTEN is not set. It is forbidden to set both TXTEN and RXTEN for a half duplex peripheral. * TXTDIS: Transmitter Transfer Disable 0 = No effect. 1 = Disables the PDC transmitter channel requests. When a half duplex peripheral is connected to the PDC, disabling the transmitter channel requests disables the receiver channel requests. 279 6384D-ATARM-04-May-09 24.4.10 Transfer Status Register Register Name: PERIPH_PTSR Access Type: 31 - 23 - 15 - 7 - Read-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 TXTEN 0 RXTEN * RXTEN: Receiver Transfer Enable 0 = PDC Receiver channel requests are disabled. 1 = PDC Receiver channel requests are enabled. * TXTEN: Transmitter Transfer Enable 0 = PDC Transmitter channel requests are disabled. 1 = PDC Transmitter channel requests are enabled. 280 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 25. Clock Generator 25.1 Overview The Clock Generator is made up of 2 PLLs, a Main Oscillator, as well as an RC Oscillator and a 32,768 Hz low-power Oscillator. It provides the following clocks: * SLCK, the Slow Clock, which is the only permanent clock within the system * MAINCK is the output of the Main Oscillator The Clock Generator User Interface is embedded within the Power Management Controller one and is described in Section 26.9. However, the Clock Generator registers are named CKGR_. * PLLACK is the output of the Divider and PLL A block * PLLBCK is the output of the Divider and PLL B block 25.2 Slow Clock Crystal Oscillator The Clock Generator integrates a 32,768 Hz low-power oscillator. The XIN32 and XOUT32 pins must be connected to a 32,768 Hz crystal. Two external capacitors must be wired as shown in Figure 25-1. Figure 25-1. Typical Slow Clock Crystal Oscillator Connection XIN32 32,768 Hz Crystal XOUT32 GNDPLL 25.3 Slow Clock RC Oscillator The user has to take into account the possible drifts of the RC Oscillator. More details are given in the section "DC Characteristics" of the product datasheet. 25.4 Main Oscillator Figure 25-2 shows the Main Oscillator block diagram. 281 6384D-ATARM-04-May-09 Figure 25-2. Main Oscillator Block Diagram MOSCEN XIN XOUT Main Oscillator MAINCK Main Clock OSCOUNT SLCK Slow Clock Main Oscillator Counter Main Clock Frequency Counter MOSCS MAINF MAINRDY 25.4.1 Main Oscillator Connections The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typical crystal connection is illustrated in Figure 25-3. For further details on the electrical characteristics of the Main Oscillator, see the section "DC Characteristics" of the product datasheet. Figure 25-3. Typical Crystal Connection AT91 Microcontroller XIN XOUT GND 1K 25.4.2 Main Oscillator Startup Time The startup time of the Main Oscillator is given in the DC Characteristics section of the product datasheet. The startup time depends on the crystal frequency and decreases when the frequency rises. Main Oscillator Control To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is selected. The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCEN bit in the Main Oscillator Register (CKGR_MOR). 25.4.3 282 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit in PMC_SR is automatically cleared, indicating the main clock is off. When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillator. This startup time depends on the crystal frequency connected to the main oscillator. When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main oscillator, the MOSCS bit in PMC_SR (Status Register) is cleared and the counter starts counting down on the slow clock divided by 8 from the OSCOUNT value. Since the OSCOUNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Setting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor. 25.4.4 Main Clock Frequency Counter The Main Oscillator features a Main Clock frequency counter that provides the quartz frequency connected to the Main Oscillator. Generally, this value is known by the system designer; however, it is useful for the boot program to configure the device with the correct clock speed, independently of the application. The Main Clock frequency counter starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock as soon as the Main Oscillator is stable, i.e., as soon as the MOSCS bit is set. Then, at the 16th falling edge of Slow Clock, the MAINRDY bit in CKGR_MCFR (Main Clock Frequency Register) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be determined. 25.4.5 Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin under these conditions are given in the product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC register (CKGR_MOR) for the external clock to operate properly. 25.5 Divider and PLL Block The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect the PLL minimum input frequency when programming the divider. Figure 25-4 shows the block diagram of the divider and PLL block. 283 6384D-ATARM-04-May-09 Figure 25-4. Divider and PLL Block Diagram DIVB MULB OUTB MAINCK Divider B PLL B PLLBCK DIVA MULA OUTA PLLACK Divider A PLL A PLLBCOUNT PLL B Counter LOCKB PLLACOUNT SLCK PLL A Counter LOCKA 25.5.1 Divider and Phase Lock Loop Programming The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 1. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0. The PLL allows multiplication of the divider's outputs. The PLL clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field. Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit (LOCKA or LOCKB) in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT or PLLBCOUNT) in CKGR_PLLR (CKGR_PLLAR or CKGR_PLLBR), are loaded in the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel. 284 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 26. Power Management Controller (PMC) 26.1 Overview The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. The Power Management Controller provides the following clocks: * MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently, such as the AIC and the Memory Controller. * Processor Clock (PCK), switched off when entering processor in idle mode. * Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, MCI, etc.) and independently controllable. In order to reduce the number of clock names in a product, the Peripheral Clocks are named MCK in the product datasheet. * UHP Clock (UHPCK), required by USB Host Port operations. * Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on the PCKx pins. 26.2 Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs. The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a Master Clock divider which allows the processor clock to be faster than the Master Clock. The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler. The Master Clock divider can be programmed through the MDIV field in PMC_MCKR. Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. 285 6384D-ATARM-04-May-09 Figure 26-1. Master Clock Controller PMC_MCKR CSS SLCK MAINCK PLLACK PLLBCK Processor Clock Divider PDIV PMC_MCKR To the Processor Clock Controller (PCK) Master Clock Prescaler Master Clock Divider MCK PMC_MCKR PRES PMC_MCKR MDIV 26.3 Processor Clock Controller The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR).The status of this clock (at least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR). The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. The PMC contains a Processor Clock divider which allows the processor clock to be divided independently of the Master Clock divider setting. The Processor Clock divider can be programmed through the PDIV field in PMC_MCKR. 26.4 USB Clock Controller The USB Source Clock is always generated from the PLL B output. If using the USB, the user must program the PLL to generate a 48 MHz or a 96 MHz signal with an accuracy of 0.25% depending on the USBDIV bit in CKGR_PLLBR (see Figure 26-2). When the PLL B output is stable, i.e., the LOCKB is set: * The USB host clock can be enabled by setting the UHP bit in PMC_SCER. To save power on this peripheral when it is not used, the user can set the UHP bit in PMC_SCDR. The UHP bit in PMC_SCSR gives the activity of this clock. The USB host port require both the 12/48 MHz signal and the Master Clock. The Master Clock may be controlled via the Master Clock Controller. 286 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 26-2. USB Clock Controller USBDIV USB Source Clock UDP Clock (UDPCK) Divider /1,/2,/4 UDP UHP Clock (UHPCK) UHP 26.5 Peripheral Clock Controller The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral Clock Controller. The user can individually enable and disable the Master Clock on the peripherals by writing into the Peripheral Clock Enable (PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR). When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset. In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system. The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 26.6 Programmable Clock Output Controller The PMC controls 2 signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers. PCKx can be independently selected between the Slow clock, the PLL A output, the PLL B output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR (System Clock Status Register). Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed. 26.7 Programming Sequence 1. Enabling the Main Oscillator: The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the CKGR_MOR register. 287 6384D-ATARM-04-May-09 Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in the PMC_IER register. Code Example: write_register(CKGR_MOR,0x00000701) Start Up Time = 8 * OSCOUNT / SLCK = 56 Slow Clock Cycles. So, the main oscillator will be enabled (MOSCS bit set) after 56 Slow Clock Cycles. 2. Checking the Main Oscillator Frequency (Optional): In some situations the user may need an accurate measure of the main oscillator frequency. This measure can be accomplished via the CKGR_MCFR register. Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF field in CKGR_MCFR register. This provides the number of main clock cycles within sixteen slow clock cycles. 3. Setting PLL A and divider A: All parameters necessary to configure PLL A and divider A are located in the CKGR_PLLAR register. It is important to note that Bit 29 must always be set to 1 when programming the CKGR_PLLAR register. The DIVA field is used to control the divider A itself. The user can program a value between 0 and 255. Divider A output is divider A input divided by DIVA. By default, DIVA parameter is set to 0 which means that divider A is turned off. The OUTA field is used to select the PLL A output frequency range. The MULA field is the PLL A multiplier factor. This parameter can be programmed between 0 and 254. If MULA is set to 0, PLL A will be turned off. Otherwise PLL A output frequency is PLL A input frequency multiplied by (MULA + 1). The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR register after CKGR_PLLAR register has been written. Once CKGR_PLLAR register has been written, the user is obliged to wait for the LOCKA bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCKA has been enabled in the PMC_IER register. All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some stage one of the following parameters, MULA, DIVA is modified, LOCKA bit will go low to indicate that PLL A is not ready yet. When PLL A is locked, LOCKA will be set again. User has to wait for LOCKA bit to be set before using the PLL A output clock. Code Example: write_register(CKGR_PLLAR,0x20030602) 288 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary PLL A input clock is main clock divided by 2. PLL An output clock is PLL A input clock multiplied by 4. Once CKGR_PLLAR has been written, LOCKA bit will be set after six slow clock cycles. 4. Setting PLL B and divider B: All parameters needed to configure PLL B and divider B are located in the CKGR_PLLBR register. The DIVB field is used to control divider B itself. A value between 0 and 255 can be programmed. Divider B output is divider B input divided by DIVB parameter. By default DIVB parameter is set to 0 which means that divider B is turned off. The OUTB field is used to select the PLL B output frequency range. The MULB field is the PLL B multiplier factor. This parameter can be programmed between 0 and 62. If MULB is set to 0, PLL B will be turned off, otherwise the PLL B output frequency is PLL B input frequency multiplied by (MULB + 1). The PLLBCOUNT field specifies the number of slow clock cycles before LOCKB bit is set in the PMC_SR register after CKGR_PLLBR register has been written. Once the PMC_PLLB register has been written, the user must wait for the LOCKB bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCKB has been enabled in the PMC_IER register. All parameters in CKGR_PLLBR can be programmed in a single write operation. If at some stage one of the following parameters, MULB, DIVB is modified, LOCKB bit will go low to indicate that PLL B is not ready yet. When PLL B is locked, LOCKB will be set again. The user is constrained to wait for LOCKB bit to be set before using the PLL A output clock. The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the USB clock(s). Code Example: write_register(CKGR_PLLBR,0x20030602) PLL B input clock is main clock divided by 2. PLL B output clock is PLL B input clock multiplied by 4. Once CKGR_PLLBR has been written, LOCKB bit will be set after six slow clock cycles. 5. Selection of Master Clock and Processor Clock The Master Clock and the Processor Clock are configurable via the PMC_MCKR register. The CSS field is used to select the clock source of the Master Clock and Processor Clock dividers. By default, the selected clock source is slow clock. The PRES field is used to control the Master/Processor Clock prescaler. The user can choose between different values (1, 2, 4, 8, 16, 32, 64). Prescaler output is the selected clock source divided by PRES parameter. By default, PRES parameter is set to 1 which means that the input clock of the Master Clock and Processor Clock dividers is equal to slow clock. 289 6384D-ATARM-04-May-09 The MDIV field is used to control the Master Clock divider. It is possible to choose between different values (0, 1, 2, 3). The Master Clock output is Master/Processor Clock Prescaler output divided by 1, 2, 4 or 6, depending on the value programmed in MDIV. The PDIV field is used to control the Processor Clock divider. It is possible to choose between different values (0, 1). The Processor Clock output is Master/Processor Clock Prescaler output divided by 1 or 2, depending on the value programmed in PDIV. By default, MDIV and PDIV are set to 0, which indicates that Processor Clock is equal to the Master Clock. Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER register. The PMC_MCKR register must not be programmed in a single write operation. The preferred programming sequence for the PMC_MCKR register is as follows: * If a new value for CSS field corresponds to PLL Clock, - Program the PRES field in the PMC_MCKR register. - Wait for the MCKRDY bit to be set in the PMC_SR register. - Program the CSS field in the PMC_MCKR register. - Wait for the MCKRDY bit to be set in the PMC_SR register. * If a new value for CSS field corresponds to Main Clock or Slow Clock, - Program the CSS field in the PMC_MCKR register. - Wait for the MCKRDY bit to be set in the PMC_SR register. - Program the PRES field in the PMC_MCKR register. - Wait for the MCKRDY bit to be set in the PMC_SR register. If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks. Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR (CKGR_PLLAR or CKGR_PLLBR), the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK (LOCKA or LOCKB) goes high and MCKRDY is set. While PLLA is unlocked, the Master Clock selection is automatically changed to Slow Clock. While PLLB is unlocked, the Master Clock selection is automatically changed to Main Clock. For further information, see Section 26.8.2. "Clock Switching Waveforms" on page 294. Code Example: write_register(PMC_MCKR,0x00000001) wait (MCKRDY=1) write_register(PMC_MCKR,0x00000011) wait (MCKRDY=1) The Master Clock is main clock divided by 16. The Processor Clock is the Master Clock. 290 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 6. Selection of Programmable clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 2 Programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which Programmable clock is enabled. By default all Programmable clocks are disabled. PMC_PCKx registers are used to configure Programmable clocks. The CSS field is used to select the Programmable clock divider source. Four clock options are available: main clock, slow clock PLLACK, PLLBCK. By default, the clock source selected is slow clock. The PRES field is used to control the Programmable clock prescaler. It is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By default, the PRES parameter is set to 1 which means that master clock is equal to slow clock. Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write operation. If the CSS and PRES parameters are to be modified, the corresponding Programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the Programmable clock and wait for the PCKRDYx bit to be set. Code Example: write_register(PMC_PCK0,0x00000015) Programmable clock 0 is main clock divided by 32. 7. Enabling Peripheral Clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCER and PMC_PCDR. Depending on the system used, 13 peripheral clocks can be enabled or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled. Note: Each enabled peripheral clock corresponds to Master Clock. Code Examples: write_register(PMC_PCER,0x00000110) 291 6384D-ATARM-04-May-09 Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010) Peripheral clock 4 is disabled. 292 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 26.8 26.8.1 Clock Switching Details Master Clock Switching Timings Table 26-1and Table 26-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 26-1. Clock Switching Timings (Worst Case) Main Clock SLCK PLL Clock From To Main Clock - 0.5 x Main Clock + 4.5 x SLCK 0.5 x Main Clock + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLLx Clock 4 x SLCK + 2.5 x Main Clock - 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK 3 x PLL Clock + 4 x SLCK + 1 x Main Clock 3 x PLL Clock + 5 x SLCK 2.5 x PLL Clock + 4 x SLCK + PLLCOUNT x SLCK SLCK PLL Clock Notes: 1. PLL designates either the PLL A or the PLL B Clock. 2. PLLCOUNT designates either PLLACOUNT or PLLBCOUNT. Table 26-2. Clock Switching Timings (Worst Case) From PLLA Clock PLLB Clock To PLLA Clock 2.5 x PLLA Clock + 4 x SLCK + PLLACOUNT x SLCK 3 x PLLB Clock + 4 x SLCK + 1.5 x PLLB Clock 3 x PLLA Clock + 4 x SLCK + 1.5 x PLLA Clock 2.5 x PLLB Clock + 4 x SLCK + PLLBCOUNT x SLCK PLLB Clock 293 6384D-ATARM-04-May-09 26.8.2 Clock Switching Waveforms Figure 26-3. Switch Master Clock from Slow Clock to PLL Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 26-4. Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR 294 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 26-5. Change PLLA Programming Slow Clock PLLA Clock LOCK MCKRDY Master Clock Slow Clock Write CKGR_PLLAR Figure 26-6. Change PLLB Programming Main Clock PLLB Clock LOCK MCKRDY Master Clock Main Clock Write CKGR_PLLBR 295 6384D-ATARM-04-May-09 Figure 26-7. Programmable Clock Output Programming PLL Clock PCKRDY PCKx Output Write PMC_PCKx PLL Clock is selected Write PMC_SCER PCKx is enabled Write PMC_SCDR PCKx is disabled 296 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 26.9 Power Management Controller (PMC) User Interface Register Mapping Register System Clock Enable Register System Clock Disable Register System Clock Status Register Reserved Peripheral Clock Enable Register Peripheral Clock Disable Register Peripheral Clock Status Register Reserved Main Oscillator Register Main Clock Frequency Register PLL A Register PLL B Register Master Clock Register Reserved Reserved Programmable Clock 0 Register Programmable Clock 1 Register Reserved Interrupt Enable Register Interrupt Disable Register Status Register Interrupt Mask Register Reserved PLL Charge Pump Current Register Name PMC_SCER PMC_SCDR PMC _SCSR - PMC _PCER PMC_PCDR PMC_PCSR - CKGR_MOR CKGR_MCFR CKGR_PLLAR CKGR_PLLBR PMC_MCKR - - PMC_PCK0 PMC_PCK1 - PMC_IER PMC_IDR PMC_SR PMC_IMR - PMC_PLLICPR Access Write-only Write-only Read-only - Write-only Write-only Read-only - Read-write Read-only Read-write Read-write Read-write - - Read-write Read-write - Write-only Write-only Read-only Read-only - Write-only Reset - - 0x03 - - - 0x0 - 0x0 0x0 0x3F00 0x3F00 0x0 - - 0x0 0x0 - --0x08 0x0 - 0x0 Table 26-3. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0038 0x003C 0x0040 0x0044 0x0048 - 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 - 0x007C 0x0080 297 6384D-ATARM-04-May-09 26.9.1 PMC System Clock Enable Register Register Name:PMC_SCER Access Type:Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PCK1 1 PCK0 0 UDP UHP - - - - - - * UHP: USB Host Port Clock Enable 0 = No effect. 1 = Enables the 12 and 48 MHz clock of the USB Host Port. * UDP: USB Device Port Clock Enable 0 = No effect. 1 = Enables the 48 MHz clock of the USB Device Port. * PCKx: Programmable Clock x Output Enable 0 = No effect. 1 = Enables the corresponding Programmable Clock output. 298 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 26.9.2 PMC System Clock Disable Register Register Name:PMC_SCDR Access Type:Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PCK1 1 PCK0 0 UDP UHP - - - - - PCK * PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor clock. This is used to enter the processor in Idle Mode. * UHP: USB Host Port Clock Disable 0 = No effect. 1 = Disables the 12 and 48 MHz clock of the USB Host Port. * UDP: USB Device Port Clock Disable 0 = No effect. 1 = Disables the 48 MHz clock of the USB Device Port. * PCKx: Programmable Clock x Output Disable 0 = No effect. 1 = Disables the corresponding Programmable Clock output. 299 6384D-ATARM-04-May-09 26.9.3 PMC System Clock Status Register Register Name:PMC_SCSR Access Type:Read-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PCK1 1 PCK0 0 UDP UHP - - - - - PCK * PCK: Processor Clock Status 0 = The Processor clock is disabled. 1 = The Processor clock is enabled. * UHP: USB Host Port Clock Status 0 = The 12 and 48 MHz clock (UHPCK) of the USB Host Port is disabled. 1 = The 12 and 48 MHz clock (UHPCK) of the USB Host Port is enabled. * UDP: USB Device Port Clock Status 0 = The 48 MHz clock (UDPCK) of the USB Device Port is disabled. 1 = The 48 MHz clock (UDPCK) of the USB Device Port is enabled. * PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled. 1 = The corresponding Programmable Clock output is enabled. 300 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 26.9.4 PMC Peripheral Clock Enable Register Register Name:PMC_PCER Access Type:Write-only 31 30 29 28 27 26 25 24 PID31 23 PID30 22 PID29 21 PID28 20 PID27 19 PID26 18 PID25 17 PID24 16 PID23 15 PID22 14 PID21 13 PID20 12 PID19 11 PID18 10 PID17 9 PID16 8 PID15 7 PID14 6 PID13 5 PID12 4 PID11 3 PID10 2 PID9 1 PID8 0 PID7 PID6 PID5 PID4 PID3 PID2 - - * PIDx: Peripheral Clock x Enable 0 = No effect. 1 = Enables the corresponding peripheral clock. Note: Note: PID2 to PID31 refer to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet. Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. 26.9.5 PMC Peripheral Clock Disable Register Register Name:PMC_PCDR Access Type:Write-only 31 30 29 28 27 26 25 24 PID31 23 PID30 22 PID29 21 PID28 20 PID27 19 PID26 18 PID25 17 PID24 16 PID23 15 PID22 14 PID21 13 PID20 12 PID19 11 PID18 10 PID17 9 PID16 8 PID15 7 PID14 6 PID13 5 PID12 4 PID11 3 PID10 2 PID9 1 PID8 0 PID7 PID6 PID5 PID4 PID3 PID2 - - * PIDx: Peripheral Clock x Disable 0 = No effect. 1 = Disables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet. 301 6384D-ATARM-04-May-09 26.9.6 PMC Peripheral Clock Status Register Register Name:PMC_PCSR Access Type:Read-only 31 30 29 28 27 26 25 24 PID31 23 PID30 22 PID29 21 PID28 20 PID27 19 PID26 18 PID25 17 PID24 16 PID23 15 PID22 14 PID21 13 PID20 12 PID19 11 PID18 10 PID17 9 PID16 8 PID15 7 PID14 6 PID13 5 PID12 4 PID11 3 PID10 2 PID9 1 PID8 0 PID7 PID6 PID5 PID4 PID3 PID2 - - * PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled. 1 = The corresponding peripheral clock is enabled. Note: PID2 to PID31 refer to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet. 302 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 26.9.7 PMC Clock Generator Main Oscillator Register Register Name:CKGR_MOR Access Type:Read-write 31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 OSCOUNT 7 - 6 - 5 - 4 - 3 - 2 - 1 OSCBYPASS 0 MOSCEN 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 * MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0 = The Main Oscillator is disabled. 1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0. When MOSCEN is set, the MOSCS flag is set once the Main Oscillator startup time is achieved. * OSCBYPASS: Oscillator Bypass 0 = No effect. 1 = The Main Oscillator is bypassed. MOSCEN must be set to 0. An external clock must be connected on XIN. When OSCBYPASS is set, the MOSCS flag in PMC_SR is automatically set. Clearing MOSCEN and OSCBYPASS bits allows resetting the MOSCS flag. * OSCOUNT: Main Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time. 303 6384D-ATARM-04-May-09 26.9.8 PMC Clock Generator Main Clock Frequency Register Register Name:CKGR_MCFR Access Type:Read-only 31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 MAINF 7 6 5 4 MAINF 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 MAINRDY 8 * MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. * MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled. 1 = The Main Oscillator has been enabled previously and MAINF value is available. 304 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 26.9.9 PMC Clock Generator PLL A Register Register Name:CKGR_PLLAR Access Type:Read-write 31 - 23 30 - 22 29 1 21 28 - 20 MULA 15 OUTA 7 6 5 4 DIVA 3 14 13 12 11 PLLACOUNT 2 1 0 10 9 8 27 - 19 26 - 18 25 - 17 24 - 16 Possible limitations on PLL A input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register. * DIVA: Divider A DIVA 0 1 2 - 255 Divider Selected Divider output is 0 Divider is bypassed Divider output is the Main Clock divided by DIVA. * PLLACOUNT: PLL A Counter Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written. * OUTA: PLL A Clock Frequency Range To optimize clock performance, this field must be programmed as specified in "PLL Characteristics" in the Electrical Characteristics section of the product datasheet. * MULA: PLL A Multiplier 0 = The PLL A is deactivated. 1 up to 254 = The PLL A Clock frequency is the PLL A input frequency multiplied by MULA + 1. 305 6384D-ATARM-04-May-09 26.9.10 PMC Clock Generator PLL B Register Register Name:CKGR_PLLBR Access Type:Read-write 31 - 23 - 15 OUTB 7 6 5 4 DIVB 3 30 - 22 - 14 29 USBDIV 21 20 28 27 - 19 MULB 13 12 11 PLLBCOUNT 2 1 0 10 9 8 26 - 18 25 - 17 24 - 16 Possible limitations on PLL B input frequencies and multiplier factors should be checked before using the PMC. * DIVB: Divider B DIVB 0 1 2 - 255 Divider Selected Divider output is 0 Divider is bypassed Divider output is the selected clock divided by DIVB. * PLLBCOUNT: PLL B Counter Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written. * OUTB: PLL B Clock Frequency Range To optimize clock performance, this field must be programmed as specified in "PLL Characteristics" in the Electrical Characteristics section of the product datasheet. * MULB: PLL B Multiplier 0 = The PLL B is deactivated. 1 up to 62 = The PLL B Clock frequency is the PLL B input frequency multiplied by MULB + 1. * USBDIV: Divider for USB Clock. USBDIV 0 0 1 1 0 1 0 1 Divider Selected Divider output is PLL B clock output Divider output is PLL B clock output divided by 2 Divider output is PLL B clock output divided by 4 Reserved 306 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 26.9.11 PMC Master Clock Register Register Name:PMC_MCKR Access Type:Read-write 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 PDIV 4 - 3 - 2 1 MDIV 0 - - - PRES CSS * CSS: Master/Processor Clock Source Selection CSS 0 0 1 1 0 1 0 1 Clock Source Selection Slow Clock is selected Main Clock is selected PLLA Clock is selected PLLB Clock is selected * PRES: Master/Processor Clock Prescaler Master/Processor Clock Dividers Input Clock 0 1 0 1 0 1 0 1 Selected clock Selected clock divided by 2 Selected clock divided by 4 Selected clock divided by 8 Selected clock divided by 16 Selected clock divided by 32 Selected clock divided by 64 Reserved PRES 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 * MDIV: Master Clock Division MDIV 0 0 1 1 0 1 0 1 Master Clock Division Master Clock is Prescaler Output Clock divided by 1. Master Clock is Prescaler Output Clock divided by 2. Master Clock is Prescaler Output Clock divided by 4. Master Clock is Prescaler Output Clock divided by 6. 307 6384D-ATARM-04-May-09 * PDIV: Processor Clock Division PDIV 0 1 Processor Clock Division Processor Clock is Prescaler Output Clock divided by 1. Processor Clock is Prescaler Output Clock divided by 2. Warning: If MDIV is written to 0, the write in PDIV is not taken in account and PDIV is forced to 0 (The Master Clock frequency cannot be superior to the Processor Clock frequency). 308 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 26.9.12 PMC Programmable Clock Register Register Name:PMC_PCKx Access Type:Read-write 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - - - PRES CSS * CSS: Master Clock Selection CSS 0 0 1 1 0 1 0 1 Clock Source Selection Slow Clock is selected Main Clock is selected PLL A Clock is selected PLL B Clock is selected * PRES: Programmable Clock Prescaler PRES 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Programmable Clock Selected clock Selected clock divided by 2 Selected clock divided by 4 Selected clock divided by 8 Selected clock divided by 16 Selected clock divided by 32 Selected clock divided by 64 Reserved 309 6384D-ATARM-04-May-09 26.9.13 PMC Interrupt Enable Register Register Name:PMC_IER Access Type:Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 7 6 5 4 3 2 PCKRDY1 1 PCKRDY0 0 - - - - MCKRDY LOCKB LOCKA MOSCS * MOSCS: Main Oscillator Status Interrupt Enable * LOCKA: PLL A Lock Interrupt Enable * LOCKB: PLL B Lock Interrupt Enable * MCKRDY: Master Clock Ready Interrupt Enable * PCKRDYx: Programmable Clock Ready x Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 310 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 26.9.14 PMC Interrupt Disable Register Register Name:PMC_IDR Access Type:Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 7 6 5 4 3 2 PCKRDY1 1 PCKRDY0 0 - - - - MCKRDY LOCKB LOCKA MOSCS * MOSCS: Main Oscillator Status Interrupt Disable * LOCKA: PLL A Lock Interrupt Disable * LOCKB: PLL B Lock Interrupt Disable * MCKRDY: Master Clock Ready Interrupt Disable * PCKRDYx: Programmable Clock Ready x Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 311 6384D-ATARM-04-May-09 26.9.15 PMC Status Register Register Name:PMC_SR Access Type:Read-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 7 6 5 4 3 2 PCKRDY1 1 PCKRDY0 0 OSC_SEL - - - MCKRDY LOCKB LOCKA MOSCS * MOSCS: Main Oscillator Status 0 = Main oscillator is not stabilized. 1 = Main oscillator is stabilized. * LOCKA: PLL A Lock Status 0 = PLL A is not locked 1 = PLL A is locked. * LOCKB: PLL B Lock Status 0 = PLL B is not locked. 1 = PLL B is locked. * MCKRDY: Master Clock Status 0 = Master Clock is not ready. 1 = Master Clock is ready. * OSC_SEL: Slow Clock Oscillator Selection 0 = Internal slow clock RC oscillator. 1 = External slow clock 32 kHz oscillator. * PCKRDYx: Programmable Clock Ready Status 0 = Programmable Clock x is not ready. 1 = Programmable Clock x is ready. 312 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 26.9.16 PMC Interrupt Mask Register Register Name:PMC_IMR Access Type:Read-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 7 6 5 4 3 2 PCKRDY1 1 PCKRDY0 0 - - - - MCKRDY LOCKB LOCKA MOSCS * MOSCS: Main Oscillator Status Interrupt Mask * LOCKA: PLL A Lock Interrupt Mask * LOCKB: PLL B Lock Interrupt Mask * MCKRDY: Master Clock Ready Interrupt Mask * PCKRDYx: Programmable Clock Ready x Interrupt Mask 0 = The corresponding interrupt is enabled. 1 = The corresponding interrupt is disabled. 313 6384D-ATARM-04-May-09 26.9.17 PLL Charge Pump Current Register Register Name:PMC_PLLICPR Access Type:Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 ICPLLB 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - - - - - - - ICPLLA * ICPLLA: Charge Pump Current To optimize clock performance, this field must be programmed as specified in "PLL A Characteristics" in the Electrical Characteristics section of the product datasheet. * ICPLLB: Charge Pump Current Must be set to 0. 314 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 27. Advanced Interrupt Controller (AIC) 27.1 Overview The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins. The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or highlevel or low-level sensitive. The fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt. 315 6384D-ATARM-04-May-09 27.2 Block Diagram Figure 27-1. Block Diagram FIQ IRQ0-IRQn AIC ARM Processor Up to Thirty-two Sources nFIQ nIRQ Embedded PeripheralEE Embedded Peripheral Embedded Peripheral APB 27.3 Application Block Diagram Figure 27-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller Embedded Peripherals External Peripherals (External Interrupts) 27.4 AIC Detailed Block Diagram Figure 27-3. AIC Detailed Block Diagram Advanced Interrupt Controller FIQ PIO Controller External Source Input Stage Fast Interrupt Controller ARM Processor nFIQ nIRQ IRQ0-IRQn PIOIRQ Internal Source Input Stage Fast Forcing Interrupt Priority Controller Processor Clock Power Management Controller User Interface Wake Up Embedded Peripherals APB 316 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 27.5 I/O Line Description I/O Line Description Pin Description Fast Interrupt Interrupt 0 - Interrupt n Type Input Input Table 27-1. Pin Name FIQ IRQ0 - IRQn 27.6 27.6.1 Product Dependencies I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path. 27.6.2 Power Management The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the Advanced Interrupt Controller behavior. The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without asserting the interrupt line of the processor, thus providing synchronization of the processor on an event. 27.6.3 Interrupt Sources The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0 cannot be used. The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system peripheral interrupt lines. When a system interrupt occurs, the service routine must first distinguish the cause of the interrupt. This is performed by reading successively the status registers of the above mentioned system peripherals. The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller. The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO Controller interrupt lines are connected to the Interrupt Sources 2 to 31. The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31. 317 6384D-ATARM-04-May-09 27.7 27.7.1 Functional Description Interrupt Source Control Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user. The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in positive edge-triggered or negative edge-triggered modes. 27.7.1.1 27.7.1.2 Interrupt Source Enabling Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers; AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set of registers conducts enabling or disabling in one instruction. The interrupt mask can be read in the AIC_IMR register. A disabled interrupt does not affect servicing of other interrupts. Interrupt Clearing and Setting All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources programmed in level-sensitive mode has no effect. The clear operation is perfunctory, as the software must perform an action to reinitialize the "memorization" circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt. The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation. (See "Priority Controller" on page 321.) The automatic clear reduces the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing feature enabled as it is considered uniquely as a FIQ source. (For further details, See "Fast Forcing" on page 325.) The automatic clear of the interrupt source 0 is performed when AIC_FVR is read. 27.7.1.3 27.7.1.4 Interrupt Status For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR (Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not. The AIC_ISR register reads the number of the current interrupt (see "Priority Controller" on page 321) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. 318 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 27.7.1.5 Internal Interrupt Source Input Stage Figure 27-4. Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Source i Level/ Edge AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller AIC_IECR Edge Detector Set Clear AIC_ISCR AIC_ICCR FF AIC_IDCR 27.7.1.6 External Interrupt Source Input Stage Figure 27-5. External Interrupt Source Input Stage High/Low AIC_SMRi SRCTYPE Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Pos./Neg. Edge Detector Set AIC_ISCR AIC_ICCR Clear AIC_IDCR AIC_IECR FF 319 6384D-ATARM-04-May-09 27.7.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: * The time the software masks the interrupts. * Occurrence, either at the processor level or at the AIC level. * The execution time of the instruction in progress when the interrupt occurs. * The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. 27.7.2.1 External Interrupt Edge Triggered Source Figure 27-6. External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) nIRQ Maximum IRQ Latency = 4 Cycles nFIQ Maximum FIQ Latency = 4 Cycles 27.7.2.2 External Interrupt Level Sensitive Source Figure 27-7. External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles 320 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 27.7.2.3 Internal Interrupt Edge Triggered Source Figure 27-8. Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active 27.7.2.4 Internal Interrupt Level Sensitive Source Figure 27-9. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 27.7.3 27.7.3.1 Normal Interrupt Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing). Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest. As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR (Source Mode Register), the nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since the nIRQ has been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software. The current priority level is defined as the priority level of the current interrupt. If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first. The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in 321 6384D-ATARM-04-May-09 progress, it is delayed until the software indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the exit point of the interrupt handling. 27.7.3.2 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written. The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. 27.7.3.3 Interrupt Vectoring The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the current interrupt is returned. This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address 0x0000 0018 through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operating system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system's general interrupt handler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. 27.7.3.4 Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and the associated status bits. It is assumed that: 322 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. The instruction at the ARM interrupt exception vector address is required to work with the vectoring LDR PC, [PC, # -&F20] When nIRQ is asserted, if the bit "I" of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four. 2. The ARM core enters Interrupt mode, if it has not already done so. 3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects: - Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt. - De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ. - Automatically clears the interrupt, if it has been programmed to be edge-triggered. - Pushes the current level and the current interrupt number on to the stack. - Returns the value written in the AIC_SVR corresponding to the current interrupt. 4. The previous step has the effect of branching to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction SUB PC, LR, #4 may be used. 5. Further interrupts can then be unmasked by clearing the "I" bit in CPSR, allowing reassertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs. 6. The interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1. Note: If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. 7. The "I" bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not immediately start because the "I" bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. Note: The "I" bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked). 323 6384D-ATARM-04-May-09 27.7.4 27.7.4.1 Fast Interrupt Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller. Fast Interrupt Control The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The field SRCTYPE of AIC_SMR0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled. 27.7.4.2 27.7.4.3 Fast Interrupt Vectoring The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR (Fast Vector Register). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM fast interrupt vector at address 0x0000 001C through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode. 27.7.4.4 Fast Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and associated status bits. Assuming that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt: LDR PC, [PC, # -&F20] 3. The user does not need nested fast interrupts. When nFIQ is asserted, if the bit "F" of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decrementing it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automati- 324 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary cally clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed. 5. The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The "F" bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the handler operation. However, this method saves the execution of a branch instruction. 27.7.4.5 Fast Forcing The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller. Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source. When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages. When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler. If the interrupt source is programmed in level-sensitive mode and an active level is sampled, Fast Forcing results in the assertion of the nFIQ line to the core. If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results in the assertion of the nFIQ line to the core. The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Register (AIC_IPR). The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0 (AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). 325 6384D-ATARM-04-May-09 All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus lost interrupts are prevented. The read of AIC_IVR does not clear the source that has the fast forcing feature enabled. The source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources. Figure 27-10. Fast Forcing Source 0 _ FIQ Input Stage AIC_IMR AIC_IPR Automatic Clear nFIQ Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR Source n Input Stage Automatic Clear AIC_IMR AIC_IPR Priority Manager nIRQ Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n. 27.7.5 Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR. This has undesirable consequences: * If an enabled interrupt with a higher priority than the current one is pending, it is stacked. * If there is no enabled pending interrupt, the spurious vector is returned. In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state. This is avoided by using the Protect Mode. Writing PROT in AIC_DCR (Debug Control Register) at 0x1 enables the Protect Mode. When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written. An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context. 326 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC: 1. Calculates active interrupt (higher than current or spurious). 2. Determines and returns the vector of the active interrupt. 3. Memorizes the interrupt. 4. Pushes the current priority level onto the internal stack. 5. Acknowledges the interrupt. However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written. Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code. 27.7.6 Spurious Interrupt The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when: * An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. * An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.) * An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt. 27.7.7 General Interrupt Mask The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution. 327 6384D-ATARM-04-May-09 27.8 Advanced Interrupt Controller (AIC) User Interface 27.8.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only a 4-Kbyte offset. Table 27-2. Offset 0x00 0x04 --0x7C 0x80 0x84 --0xFC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 - 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C 0x140 0x144 0x148 0x14C - 0x1E0 0x1EC - 0x1FC Notes: Register Mapping Register Source Mode Register 0 Source Mode Register 1 --Source Mode Register 31 Source Vector Register 0 Source Vector Register 1 --Source Vector Register 31 Interrupt Vector Register FIQ Interrupt Vector Register Interrupt Status Register Interrupt Pending Register Interrupt Mask Register(2) Core Interrupt Status Register Reserved Interrupt Enable Command Register (2) (2) (2) Name AIC_SMR0 AIC_SMR1 --AIC_SMR31 AIC_SVR0 AIC_SVR1 --AIC_SVR31 AIC_IVR AIC_FVR AIC_ISR AIC_IPR AIC_IMR AIC_CISR --AIC_IECR AIC_IDCR AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU AIC_DCR --(2) (2) Access Read-write Read-write --Read-write Read-write Read-write --Read-write Read-only Read-only Read-only Read-only Read-only Read-only --Write-only Write-only Write-only Write-only Write-only Read-write Read-write --Write-only Write-only Read-only --- Reset 0x0 0x0 --0x0 0x0 0x0 --0x0 0x0 0x0 0x0 0x0(1) 0x0 0x0 ------------0x0 0x0 ------0x0 --- Interrupt Disable Command Register Interrupt Clear Command Register(2) Interrupt Set Command Register (2) End of Interrupt Command Register Spurious Interrupt Vector Register Debug Control Register Reserved Fast Forcing Enable Register Fast Forcing Disable Register Reserved Reserved AIC_FFER AIC_FFDR AIC_FFSR --- Fast Forcing Status Register(2) 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet. 3. Values in the Version Register vary with the version of the IP block implementation. 328 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 27.8.2 AIC Source Mode Register Register Name: AIC_SMR0..AIC_SMR31 Access Type: Reset Value: 31 - 23 - 15 - 7 - Read-write 0x0 30 - 22 - 14 - 6 SRCTYPE 29 - 21 - 13 - 5 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 25 - 17 - 9 - 1 PRIOR 24 - 16 - 8 - 0 * PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ in the related SMR register AIC_SMRx. * SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt sources. SRCTYPE 0 0 1 1 0 1 0 1 Internal Interrupt Sources High level Sensitive Positive edge triggered High level Sensitive Positive edge triggered External Interrupt Sources Low level Sensitive Negative edge triggered High level Sensitive Positive edge triggered 329 6384D-ATARM-04-May-09 27.8.3 AIC Source Vector Register Register Name: AIC_SVR0..AIC_SVR31 Access Type: Reset Value: 31 Read-write 0x0 30 29 28 VECTOR 27 26 25 24 23 22 21 20 VECTOR 19 18 17 16 15 14 13 12 VECTOR 11 10 9 8 7 6 5 4 VECTOR 3 2 1 0 * VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source. 330 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 27.8.4 AIC Interrupt Vector Register Register Name: AIC_IVR Access Type: Reset Value: 31 Read-only 0x0 30 29 28 IRQV 27 26 25 24 23 22 21 20 IRQV 19 18 17 16 15 14 13 12 IRQV 11 10 9 8 7 6 5 4 IRQV 3 2 1 0 * IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. 27.8.5 AIC FIQ Vector Register Register Name: AIC_FVR Access Type: Reset Value: 31 Read-only 0x0 30 29 28 FIQV 27 26 25 24 23 22 21 20 FIQV 19 18 17 16 15 14 13 12 FIQV 11 10 9 8 7 6 5 4 FIQV 3 2 1 0 * FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. 331 6384D-ATARM-04-May-09 27.8.6 AIC Interrupt Status Register Register Name: AIC_ISR Access Type: Reset Value: 31 - 23 - 15 - 7 - Read-only 0x0 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 27 - 19 - 11 - 3 26 - 18 - 10 - 2 IRQID 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. 27.8.7 AIC Interrupt Pending Register Register Name: AIC_IPR Access Type: Reset Value: 31 PID31 23 PID23 15 PID15 7 PID7 Read-only 0x0 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ * FIQ, SYS, PID2-PID31: Interrupt Pending 0 = Corresponding interrupt is not pending. 1 = Corresponding interrupt is pending. 332 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 27.8.8 AIC Interrupt Mask Register Register Name: AIC_IMR Access Type: Reset Value: 31 PID31 23 PID23 15 PID15 7 PID7 Read-only 0x0 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ * FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled. 333 6384D-ATARM-04-May-09 27.8.9 AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Reset Value: 31 - 23 - 15 - 7 - Read-only 0x0 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 NIRQ 24 - 16 - 8 - 0 NFIQ * NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. * NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active. 334 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 27.8.10 AIC Interrupt Enable Command Register Register Name: AIC_IECR Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ * FIQ, SYS, PID2-PID31: Interrupt Enable 0 = No effect. 1 = Enables corresponding interrupt. 335 6384D-ATARM-04-May-09 27.8.11 AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ * FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect. 1 = Disables corresponding interrupt. 27.8.12 AIC Interrupt Clear Command Register Register Name: AIC_ICCR Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ * FIQ, SYS, PID2-PID31: Interrupt Clear 0 = No effect. 1 = Clears corresponding interrupt. 336 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 27.8.13 AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ * FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt. 27.8.14 AIC End of Interrupt Command Register Register Name: AIC_EOICR Access Type: 31 - 23 - 15 - 7 - Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. 337 6384D-ATARM-04-May-09 27.8.15 AIC Spurious Interrupt Vector Register Register Name: AIC_SPU Access Type: Reset Value: 31 Read-write 0x0 30 29 28 SIVR 27 26 25 24 23 22 21 20 SIVR 19 18 17 16 15 14 13 12 SIVR 11 10 9 8 7 6 5 4 SIVR 3 2 1 0 * SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt. 27.8.16 AIC Debug Control Register Register Name: AIC_DCR Access Type: Reset Value: 31 - 23 - 15 - 7 - Read-write 0x0 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 GMSK 24 - 16 - 8 - 0 PROT * PROT: Protection Mode 0 = The Protection Mode is disabled. 1 = The Protection Mode is enabled. * GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC. 1 = The nIRQ and nFIQ lines are tied to their inactive state. 338 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 27.8.17 AIC Fast Forcing Enable Register Register Name: AIC_FFER Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 - * SYS, PID2-PID31: Fast Forcing Enable 0 = No effect. 1 = Enables the fast forcing feature on the corresponding interrupt. 339 6384D-ATARM-04-May-09 27.8.18 AIC Fast Forcing Disable Register Register Name: AIC_FFDR Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 - * SYS, PID2-PID31: Fast Forcing Disable 0 = No effect. 1 = Disables the Fast Forcing feature on the corresponding interrupt. 27.8.19 AIC Fast Forcing Status Register Register Name: AIC_FFSR Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Read-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 - * SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt. 1 = The Fast Forcing feature is enabled on the corresponding interrupt. 340 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 28. Debug Unit (DBGU) 28.1 Overview The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel's ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used stand-alone for general purpose serial communication. Moreover, the association with two peripheral data controller channels permits packet handling for these tasks with processor time reduced to a minimum. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. Moreover, the association with two peripheral data controller channels permits packet handling for these tasks with processor time reduced to a minimum. The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the ARM processor visible to the software. These signals indicate the status of the DCC read and write registers and generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control. Chip Identifier registers permit recognition of the device and its revision. These registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent access to the system via the In-circuit Emulator. This permits protection of the code, stored in ROM. 341 6384D-ATARM-04-May-09 28.2 Block Diagram Figure 28-1. Debug Unit Functional Block Diagram Peripheral Bridge Peripheral DMA Controller APB Debug Unit DTXD Transmit Power Management Controller MCK Baud Rate Generator Receive Parallel Input/ Output DRXD COMMRX ARM Processor nTRST COMMTX DCC Handler Chip ID ICE Access Handler Power-on Reset force_ntrst Interrupt Control dbgu_irq Figure 28-2. Table 28-1. Pin Name DRXD DTXD Debug Unit Pin Description Description Debug Receive Data Debug Transmit Data Type Input Output 342 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 28-3. Debug Unit Application Example Boot Program Debug Monitor Trace Manager Debug Unit RS232 Drivers Programming Tool Debug Console Trace Console 28.3 28.3.1 Product Dependencies I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. 28.3.2 Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1. Interrupt Source Depending on product integration, the Debug Unit interrupt line is connected to one of the interrupt sources of the Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug Unit. Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in Figure 28-1. This sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered. 28.3.3 28.4 UART Operations The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit character handling (with parity). It has no clock pin. The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible with those of a standard USART. 28.4.1 Baud Rate Generator The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. The baud rate clock is the master clock divided by 16 times the value (CD) written in DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x 65536). 343 6384D-ATARM-04-May-09 MCK Baud Rate = --------------------16 x CD Figure 28-4. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 0 Receiver Sampling Clock Divide by 16 Baud Rate Clock 28.4.2 28.4.2.1 Receiver Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost. 28.4.2.2 Start Detection and Data Sampling The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. 344 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 28-5. Start Bit Detection Sampling Clock DRXD True Start Detection Baud Rate Clock D0 Figure 28-6. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 28.4.2.3 Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 28-7. Receiver Ready DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P S D0 D1 D2 D3 D4 D5 D6 D7 P RXRDY Read DBGU_RHR 28.4.2.4 Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 28-8. Receiver Overrun DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY OVRE RSTSTA 28.4.2.5 Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity 345 6384D-ATARM-04-May-09 bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 28-9. Parity Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit RSTSTA 28.4.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 28-10. Receiver Framing Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY FRAME Stop Bit Detected at 0 RSTSTA 28.4.3 28.4.3.1 Transmitter Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters. 28.4.3.2 Transmit Format The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field 346 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 28-11. Character Transmission Example: Parity enabled Baud Rate Clock DTXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 28.4.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed. Figure 28-12. Transmitter Control DBGU_THR Data 0 Data 1 Shift Register Data 0 Data 1 DTXD S Data 0 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR 28.4.4 Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt. 347 6384D-ATARM-04-May-09 The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a data in DBGU_THR. 28.4.5 Test Modes The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission. Figure 28-13. Test Modes Automatic Echo Receiver RXD Transmitter Disabled TXD Local Loopback Receiver Disabled RXD VDD Transmitter Disabled TXD Remote Loopback Receiver VDD Disabled RXD Transmitter Disabled TXD 28.4.6 Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator. 348 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side. As a reminder, the following instructions are used to read and write the Debug Communication Channel: MRC p14, 0, Rd, c1, c0, 0 Returns the debug communication data read register into Rd MCR p14, 0, Rd, c1, c0, 0 Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. 28.4.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields: * EXT - shows the use of the extension identifier register * NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size * ARCH - identifies the set of embedded peripherals * SRAMSIZ - indicates the size of the embedded SRAM * EPROC - indicates the embedded ARM processor * VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0. 28.4.8 ICE Access Prevention The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible. 349 6384D-ATARM-04-May-09 28.5 Debug Unit (DBGU) User Interface Register Mapping Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Receive Holding Register Transmit Holding Register Baud Rate Generator Register Reserved Chip ID Register Chip ID Extension Register Force NTRST Register Reserved PDC Area Name DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR DBGU_SR DBGU_RHR DBGU_THR DBGU_BRGR - DBGU_CIDR DBGU_EXID DBGU_FNR - - Access Write-only Read-write Write-only Write-only Read-only Read-only Read-only Write-only Read-write - Read-only Read-only Read-write - - Reset - 0x0 - - 0x0 - 0x0 - 0x0 - - - 0x0 - - Table 28-2. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 - 0x003C 0x0040 0x0044 0x0048 0x004C - 0x00FC 0x0100 - 0x0124 350 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 28.5.1 Name: Debug Unit Control Register DBGU_CR Access Type: Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 RSTSTA 0 - 7 TXDIS - 6 TXEN - 5 RXDIS - 4 RXEN - 3 RSTTX - 2 RSTRX - 1 - - * RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted. * RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. * RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0. * RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. * TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0. * TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. * RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR. 351 6384D-ATARM-04-May-09 28.5.2 Name: Debug Unit Mode Register DBGU_MR Access Type: Read-write 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 CHMODE 7 - 14 - 13 - 12 - 11 - 10 PAR - 9 - 8 - 6 5 - 4 3 - 1 0 2 - - - - - - - - * PAR: Parity Type PAR 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Parity Type Even parity Odd parity Space: parity forced to 0 Mark: parity forced to 1 No parity * CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo Local Loopback Remote Loopback 352 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 28.5.3 Name: Debug Unit Interrupt Enable Register DBGU_IER Access Type: Write-only 31 COMMRX 23 30 COMMTX 22 29 28 27 26 25 24 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 4 ENDTX - 11 TXBUFE 3 ENDRX - 10 - 9 TXEMPTY 1 TXRDY - 8 - 7 PARE - 6 FRAME - 5 OVRE - 2 - 0 RXRDY - * RXRDY: Enable RXRDY Interrupt * TXRDY: Enable TXRDY Interrupt * ENDRX: Enable End of Receive Transfer Interrupt * ENDTX: Enable End of Transmit Interrupt * OVRE: Enable Overrun Error Interrupt * FRAME: Enable Framing Error Interrupt * PARE: Enable Parity Error Interrupt * TXEMPTY: Enable TXEMPTY Interrupt * TXBUFE: Enable Buffer Empty Interrupt * RXBUFF: Enable Buffer Full Interrupt * COMMTX: Enable COMMTX (from ARM) Interrupt * COMMRX: Enable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Enables the corresponding interrupt. 353 6384D-ATARM-04-May-09 28.5.4 Name: Debug Unit Interrupt Disable Register DBGU_IDR Access Type: Write-only 31 COMMRX 23 30 COMMTX 22 29 28 27 26 25 24 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 4 ENDTX - 11 TXBUFE 3 ENDRX - 10 - 9 TXEMPTY 1 TXRDY - 8 - 7 PARE - 6 FRAME - 5 OVRE - 2 - 0 RXRDY - * RXRDY: Disable RXRDY Interrupt * TXRDY: Disable TXRDY Interrupt * ENDRX: Disable End of Receive Transfer Interrupt * ENDTX: Disable End of Transmit Interrupt * OVRE: Disable Overrun Error Interrupt * FRAME: Disable Framing Error Interrupt * PARE: Disable Parity Error Interrupt * TXEMPTY: Disable TXEMPTY Interrupt * TXBUFE: Disable Buffer Empty Interrupt * RXBUFF: Disable Buffer Full Interrupt * COMMTX: Disable COMMTX (from ARM) Interrupt * COMMRX: Disable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Disables the corresponding interrupt. 354 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 28.5.5 Name: Debug Unit Interrupt Mask Register DBGU_IMR Access Type: Read-only 31 COMMRX 23 30 COMMTX 22 29 28 27 26 25 24 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 4 ENDTX - 11 TXBUFE 3 ENDRX - 10 - 9 TXEMPTY 1 TXRDY - 8 - 7 PARE - 6 FRAME - 5 OVRE - 2 - 0 RXRDY - * RXRDY: Mask RXRDY Interrupt * TXRDY: Disable TXRDY Interrupt * ENDRX: Mask End of Receive Transfer Interrupt * ENDTX: Mask End of Transmit Interrupt * OVRE: Mask Overrun Error Interrupt * FRAME: Mask Framing Error Interrupt * PARE: Mask Parity Error Interrupt * TXEMPTY: Mask TXEMPTY Interrupt * TXBUFE: Mask TXBUFE Interrupt * RXBUFF: Mask RXBUFF Interrupt * COMMTX: Mask COMMTX Interrupt * COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 355 6384D-ATARM-04-May-09 28.5.6 Name: Debug Unit Status Register DBGU_SR Access Type: Read-only 31 COMMRX 23 30 COMMTX 22 29 28 27 26 25 24 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 4 ENDTX - 11 TXBUFE 3 ENDRX - 10 - 9 TXEMPTY 1 TXRDY - 8 - 7 PARE - 6 FRAME - 5 OVRE - 2 - 0 RXRDY - * RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled. 1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read. * TXRDY: Transmitter Ready 0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1 = There is no character written to DBGU_THR not yet transferred to the Shift Register. * ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active. * ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active. * OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA. * FRAME: Framing Error 0 = No framing error has occurred since the last RSTSTA. 1 = At least one framing error has occurred since the last RSTSTA. * PARE: Parity Error 0 = No parity error has occurred since the last RSTSTA. 1 = At least one parity error has occurred since the last RSTSTA. * TXEMPTY: Transmitter Empty 0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter. 356 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active. * RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active. * COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active. * COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive. 1 = COMMRX from the ARM processor is active. 357 6384D-ATARM-04-May-09 28.5.7 Name: Debug Unit Receiver Holding Register DBGU_RHR Access Type: Read-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 RXCHR - 3 - 2 - 1 - 0 * RXCHR: Received Character Last received character if RXRDY is set. 28.5.8 Name: Debug Unit Transmit Holding Register DBGU_THR Access Type: Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 TXCHR - 3 - 2 - 1 - 0 * TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 358 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 28.5.9 Name: Debug Unit Baud Rate Generator Register DBGU_BRGR Access Type: Read-write 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 CD - 11 - 10 - 9 - 8 7 6 5 4 CD 3 2 1 0 * CD: Clock Divisor CD 0 1 2 to 65535 Baud Rate Clock Disabled MCK MCK / (CD x 16) 359 6384D-ATARM-04-May-09 28.5.10 Name: Debug Unit Chip ID Register DBGU_CIDR Access Type:Read-only 31 EXT 23 22 ARCH 15 14 NVPSIZ2 7 6 EPROC 5 4 3 2 VERSION 13 12 11 10 NVPSIZ 1 0 30 29 NVPTYP 21 20 19 18 SRAMSIZ 9 8 28 27 26 ARCH 17 16 25 24 * VERSION: Version of the Device Current version of the device. * EPROC: Embedded Processor EPROC 0 0 1 1 0 1 0 0 1 0 0 1 Processor ARM946ES ARM7TDMI ARM920T ARM926EJS * NVPSIZ: Nonvolatile Program Memory Size NVPSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes 360 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary NVPSIZ 1 1 1 1 1 1 0 1 1 1 0 1 Size Reserved 2048K bytes Reserved * NVPSIZ2 Second Nonvolatile Program Memory Size NVPSIZ2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved * SRAMSIZ: Internal SRAM Size SRAMSIZ 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Size Reserved 1K bytes 2K bytes 6K bytes 112K bytes 4K bytes 80K bytes 160K bytes 8K bytes 16K bytes 32K bytes 64K bytes 361 6384D-ATARM-04-May-09 SRAMSIZ 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 Size 128K bytes 256K bytes 96K bytes 512K bytes * ARCH: Architecture Identifier ARCH Hex 0x19 0x29 0x34 0x37 0x39 0x3B 0x40 0x42 0x55 0x60 0x61 0x63 0x70 0x71 0x72 0x73 0x75 0x92 0xF0 Bin 0001 1001 0010 1001 0011 0100 0011 0111 0011 1001 0011 1011 0100 0000 0100 0010 0101 0101 0110 0000 0110 0001 0110 0011 0111 0000 0111 0001 0111 0010 0111 0011 0111 0101 1001 0010 1111 0000 Architecture AT91SAM9xx Series AT91SAM9XExx Series AT91x34 Series CAP7 Series CAP9 Series CAP11 Series AT91x40 Series AT91x42 Series AT91x55 Series AT91SAM7Axx Series AT91SAM7AQxx Series AT91x63 Series AT91SAM7Sxx Series AT91SAM7XCxx Series AT91SAM7SExx Series AT91SAM7Lxx Series AT91SAM7Xxx Series AT91x92 Series AT75Cxx Series * NVPTYP: Nonvolatile Program Memory Type NVPTYP 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 Memory ROM ROMless or on-chip Flash SRAM emulating ROM Embedded Flash Memory ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size 362 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists. 363 6384D-ATARM-04-May-09 28.5.11 Name: Debug Unit Chip ID Extension Register DBGU_EXID Access Type: Read-only 31 30 29 28 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 * EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0. 28.5.12 Name: Debug Unit Force NTRST Register DBGU_FNR Access Type:Read-write 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 FNTRST - - - - - - - * FNTRST: Force NTRST 0 = NTRST of the ARM processor's TAP controller is driven by the power_on_reset signal. 1 = NTRST of the ARM processor's TAP controller is held low. 364 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 29. Parallel Input Output Controller (PIO) 29.1 Overview The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features: * An input change interrupt enabling level change detection on any I/O line. * A glitch filter providing rejection of pulses lower than one-half of clock cycle. * Multi-drive capability similar to an open drain I/O line. * Control of the pull-up of the I/O line. * Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation. 365 6384D-ATARM-04-May-09 29.2 Block Diagram Figure 29-1. Block Diagram PIO Controller AIC PIO Interrupt PMC PIO Clock Data, Enable Embedded Peripheral Up to 32 peripheral IOs PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Figure 29-2. Application Block Diagram On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals PIO Controller Keyboard Driver General Purpose I/Os External Devices 366 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 29.3 29.3.1 Product Dependencies Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product. External Interrupt Lines The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs. Power Management The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available. Note that the Input Change Interrupt and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information. 29.3.2 29.3.3 29.3.4 Interrupt Generation For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled. 367 6384D-ATARM-04-May-09 29.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 29-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 29-3. I/O Line Control Logic PIO_OER[0] PIO_OSR[0] PIO_ODR[0] 1 PIO_PUER[0] PIO_PUSR[0] PIO_PUDR[0] Peripheral A Output Enable Peripheral B Output Enable PIO_ASR[0] PIO_ABSR[0] PIO_BSR[0] Peripheral A Output Peripheral B Output 0 0 0 1 PIO_PER[0] PIO_PSR[0] PIO_PDR[0] 0 0 1 PIO_MDER[0] PIO_MDSR[0] PIO_MDDR[0] 0 1 1 PIO_SODR[0] PIO_ODSR[0] PIO_CODR[0] Pad 1 Peripheral A Input Peripheral B Input PIO_PDSR[0] 0 Edge Detector Glitch Filter PIO_IFER[0] PIO_IFSR[0] PIO_IFDR[0] PIO_IER[0] 1 PIO_ISR[0] (Up to 32 possible inputs) PIO Interrupt PIO_IMR[0] PIO_IDR[0] PIO_ISR[31] PIO_IER[31] PIO_IMR[31] PIO_IDR[31] 368 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 29.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pullup Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0. 29.4.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device. 29.4.3 Peripheral A or B Selection The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected. Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR. 29.4.4 Output Control When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). 369 6384D-ATARM-04-May-09 The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 29.4.5 Synchronous Data Output Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OWSR (Output Write Status Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0. 29.4.6 Multi Drive Control (Open Drain) Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. 29.4.7 Output Line Timings Figure 29-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 29-4 also shows when the feedback in PIO_PDSR is available. 370 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 29-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 Write PIO_CODR Write PIO_ODSR at 0 APB Access APB Access PIO_ODSR 2 cycles PIO_PDSR 2 cycles 29.4.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 29.4.9 Input Glitch Filtering Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in Figure 29-5. The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled. 371 6384D-ATARM-04-May-09 Figure 29-5. Input Glitch Filter Timing MCK up to 1.5 cycles Pin Level 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles PIO_PDSR if PIO_IFSR = 1 up to 2.5 cycles 1 cycle up to 2 cycles 1 cycle 1 cycle 1 cycle 29.4.10 Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. Figure 29-6. Input Change Interrupt Timings MCK Pin Level PIO_ISR Read PIO_ISR APB Access APB Access 29.5 I/O Lines Programming Example The programing example as shown in Table 29-1 below is used to define the following configuration. * 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor 372 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor * Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts * Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter * I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor * I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor * I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor Table 29-1. Programming Example Register PIO_PER PIO_PDR PIO_OER PIO_ODR PIO_IFER PIO_IFDR PIO_SODR PIO_CODR PIO_IER PIO_IDR PIO_MDER PIO_MDDR PIO_PUDR PIO_PUER PIO_ASR PIO_BSR PIO_OWER PIO_OWDR Value to be Written 0x0000 FFFF 0x0FFF 0000 0x0000 00FF 0x0FFF FF00 0x0000 0F00 0x0FFF F0FF 0x0000 0000 0x0FFF FFFF 0x0F00 0F00 0x00FF F0FF 0x0000 000F 0x0FFF FFF0 0x00F0 00F0 0x0F0F FF0F 0x0F0F 0000 0x00F0 0000 0x0000 000F 0x0FFF FFF0 373 6384D-ATARM-04-May-09 29.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 29-2. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C Register Mapping Register PIO Enable Register PIO Disable Register PIO Status Register Reserved Output Enable Register Output Disable Register Output Status Register Reserved Glitch Input Filter Enable Register Glitch Input Filter Disable Register Glitch Input Filter Status Register Reserved Set Output Data Register Clear Output Data Register Output Data Status Register Pin Data Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register(4) Multi-driver Enable Register Multi-driver Disable Register Multi-driver Status Register Reserved Pull-up Disable Register Pull-up Enable Register Pad Pull-up Status Register Reserved PIO_PUDR PIO_PUER PIO_PUSR Write-only Write-only Read-only - - 0x00000000 PIO_SODR PIO_CODR PIO_ODSR PIO_PDSR PIO_IER PIO_IDR PIO_IMR PIO_ISR PIO_MDER PIO_MDDR PIO_MDSR Write-only Write-only Read-only or(2) Read-write Read-only Write-only Write-only Read-only Read-only Write-only Write-only Read-only - (3) Name PIO_PER PIO_PDR PIO_PSR Access Write-only Write-only Read-only Reset - - (1) PIO_OER PIO_ODR PIO_OSR Write-only Write-only Read-only - - 0x0000 0000 PIO_IFER PIO_IFDR PIO_IFSR Write-only Write-only Read-only - - 0x0000 0000 - - - 0x00000000 0x00000000 - - 0x00000000 374 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 29-2. Offset 0x0070 0x0074 0x0078 0x007C to 0x009C 0x00A0 0x00A4 0x00A8 0x00AC Notes: Register Mapping (Continued) Register Peripheral A Select Register Peripheral B Select Register AB Status Register Reserved Output Write Enable Output Write Disable Output Write Status Register Reserved PIO_OWER PIO_OWDR PIO_OWSR Write-only Write-only Read-only - - 0x00000000 (5) (5) (5) Name PIO_ASR PIO_BSR PIO_ABSR Access Write-only Write-only Read-only Reset - - 0x00000000 1. Reset value of PIO_PSR depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register. 375 6384D-ATARM-04-May-09 29.6.1 Name: PIO Controller PIO Enable Register PIO_PER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 29.6.2 Name: PIO Controller PIO Disable Register PIO_PDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: PIO Disable 0 = No effect. 1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). 376 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 29.6.3 Name: PIO Controller PIO Status Register PIO_PSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active). 1 = PIO is active on the corresponding I/O line (peripheral is inactive). 29.6.4 Name: PIO Controller Output Enable Register PIO_OER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Enable 0 = No effect. 1 = Enables the output on the I/O line. 377 6384D-ATARM-04-May-09 29.6.5 Name: PIO Controller Output Disable Register PIO_ODR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line. 29.6.6 Name: PIO Controller Output Status Register PIO_OSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Status 0 = The I/O line is a pure input. 1 = The I/O line is enabled in output. 378 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 29.6.7 Name: PIO Controller Input Filter Enable Register PIO_IFER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line. 29.6.8 Name: PIO Controller Input Filter Disable Register PIO_IFDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Filter Disable 0 = No effect. 1 = Disables the input glitch filter on the I/O line. 379 6384D-ATARM-04-May-09 29.6.9 Name: PIO Controller Input Filter Status Register PIO_IFSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line. 29.6.10 Name: PIO Controller Set Output Data Register PIO_SODR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Set Output Data 0 = No effect. 1 = Sets the data to be driven on the I/O line. 380 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 29.6.11 Name: PIO Controller Clear Output Data Register PIO_CODR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line. 29.6.12 Name: PIO Controller Output Data Status Register PIO_ODSR Read-only or Read-write 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Data Status 0 = The data to be driven on the I/O line is 0. 1 = The data to be driven on the I/O line is 1. 381 6384D-ATARM-04-May-09 29.6.13 Name: PIO Controller Pin Data Status Register PIO_PDSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1. 29.6.14 Name: PIO Controller Interrupt Enable Register PIO_IER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Change Interrupt Enable 0 = No effect. 1 = Enables the Input Change Interrupt on the I/O line. 382 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 29.6.15 Name: PIO Controller Interrupt Disable Register PIO_IDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line. 29.6.16 Name: PIO Controller Interrupt Mask Register PIO_IMR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Change Interrupt Mask 0 = Input Change Interrupt is disabled on the I/O line. 1 = Input Change Interrupt is enabled on the I/O line. 383 6384D-ATARM-04-May-09 29.6.17 Name: PIO Controller Interrupt Status Register PIO_ISR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 29.6.18 Name: PIO Multi-driver Enable Register PIO_MDER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Multi Drive Enable. 0 = No effect. 1 = Enables Multi Drive on the I/O line. 384 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 29.6.19 Name: PIO Multi-driver Disable Register PIO_MDDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Multi Drive Disable. 0 = No effect. 1 = Disables Multi Drive on the I/O line. 29.6.20 Name: PIO Multi-driver Status Register PIO_MDSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Multi Drive Status. 0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only. 385 6384D-ATARM-04-May-09 29.6.21 Name: PIO Pull Up Disable Register PIO_PUDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Pull Up Disable. 0 = No effect. 1 = Disables the pull up resistor on the I/O line. 29.6.22 Name: PIO Pull Up Enable Register PIO_PUER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Pull Up Enable. 0 = No effect. 1 = Enables the pull up resistor on the I/O line. 386 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 29.6.23 Name: PIO Pull Up Status Register PIO_PUSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line. 29.6.24 Name: PIO Peripheral A Select Register PIO_ASR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Peripheral A Select. 0 = No effect. 1 = Assigns the I/O line to the Peripheral A function. 387 6384D-ATARM-04-May-09 29.6.25 Name: PIO Peripheral B Select Register PIO_BSR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Peripheral B Select. 0 = No effect. 1 = Assigns the I/O line to the peripheral B function. 29.6.26 Name: PIO Peripheral A B Status Register PIO_ABSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Peripheral A B Status. 0 = The I/O line is assigned to the Peripheral A. 1 = The I/O line is assigned to the Peripheral B. 388 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 29.6.27 Name: PIO Output Write Enable Register PIO_OWER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Write Enable. 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line. 29.6.28 Name: PIO Output Write Disable Register PIO_OWDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Write Disable. 0 = No effect. 1 = Disables writing PIO_ODSR for the I/O line. 389 6384D-ATARM-04-May-09 29.6.29 Name: PIO Output Write Status Register PIO_OWSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line. 390 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 30. Serial Peripheral Interface (SPI) 30.1 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the "master"' which controls the data flow, while the other devices act as "slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: * Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). * Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. * Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. * Slave Select (NSS): This control line allows slaves to be turned on and off by hardware. 391 6384D-ATARM-04-May-09 30.2 Block Diagram Figure 30-1. Block Diagram PDC APB SPCK MISO MCK SPI Interface PIO MOSI NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 PMC SPI Interrupt 30.3 Application Block Diagram Figure 30-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI SPI Master NPCS0 NPCS1 NPCS2 NPCS3 NC SPCK MISO Slave 0 MOSI NSS SPCK MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS 392 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 30.4 Signal Description Signal Description Type Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select Master Input Output Output Output Output Slave Output Input Input Unused Input Table 30-1. 30.5 30.5.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. 30.5.2 Power Management The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. Interrupt The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the SPI interrupt requires programming the AIC before configuring the SPI. 30.5.3 393 6384D-ATARM-04-May-09 30.6 30.6.1 Functional Description Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode. 30.6.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 30-2 shows the four modes and corresponding parameter settings. Table 30-2. SPI Bus Protocol Mode SPI Mode 0 1 2 3 CPOL 0 0 1 1 NCPHA 1 0 1 0 Figure 30-3 and Figure 30-4 show examples of data transfers. 394 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 30-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8 SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) MSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 30-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8 SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) * MSB 6 5 4 3 2 1 LSB NSS (to slave) * Not defined but normally LSB of previous character transmitted. 30.6.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) 395 6384D-ATARM-04-May-09 connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. Before writing the TDR, the PCS field must be set in order to select a slave. If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 30-5 on page 397 shows a block diagram of the SPI when operating in Master Mode. Figure 30-6 on page 398 shows a flow chart describing how transfers are handled. 396 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 30.6.3.1 Master Mode Block Diagram Figure 30-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL MISO LSB SPI_RDR RD RDRF OVRES Shift Register MSB MOSI SPI_TDR TD SPI_CSR0..3 SPI_RDR CSAAT PS SPI_MR PCS 0 SPI_TDR PCS 1 NPCS0 PCSDEC Current Peripheral PCS NPCS3 NPCS2 NPCS1 TDRE MSTR NPCS0 MODFDIS MODF 397 6384D-ATARM-04-May-09 30.6.3.2 Master Mode Flow Diagram Figure 30-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0. 1 TDRE ? 0 1 CSAAT ? PS ? Variable peripheral yes 0 Fixed peripheral 0 0 PS ? Variable peripheral NPCS = SPI_MR(PCS) Fixed peripheral 1 SPI_TDR(PCS) = NPCS ? no NPCS = 0xF SPI_MR(PCS) = NPCS ? no NPCS = 0xF 1 NPCS = SPI_TDR(PCS) Delay DLYBCS Delay DLYBCS NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS), SPI_TDR(PCS) Delay DLYBS Serializer = SPI_TDR(TD) TDRE = 1 Data Transfer SPI_RDR(RD) = Serializer RDRF = 1 Delay DLYBCT 0 TDRE ? 1 1 CSAAT ? 0 NPCS = 0xF Delay DLYBCS 398 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 30.6.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 30.6.3.4 Transfer Delays Figure 30-7 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms: * The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one. * The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted. * The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 30-7. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 30.6.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: * Fixed Peripheral Select: SPI exchanges data with only one peripheral 399 6384D-ATARM-04-May-09 * Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect. Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 30.6.3.6 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 30.6.3.7 Peripheral Deselection When operating normally, as soon as the transfer of the last data written in SPI_TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. 400 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 30-8. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 CSAAT = 1 and CSNAAT= 0 / 1 TDRE DLYBCT A DLYBCS PCS = A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write SPI_TDR TDRE DLYBCT A DLYBCS PCS=A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] DLYBCT A DLYBCS PCS = B B A DLYBCT B DLYBCS PCS = B Write SPI_TDR 30.6.3.8 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open drain through the PIO controller, so that external pull up resistors are needed to guarantee high level. When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1. By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR). 30.6.4 SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the 401 6384D-ATARM-04-May-09 SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode. The bits are shifted out on the MISO line and sampled on the MOSI line. When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0. When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. Figure 30-9 shows a block diagram of the SPI when operating in Slave Mode. Figure 30-9. Slave Mode Functional Block Diagram SPCK NSS SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RD RDRF OVRES SPI Clock Shift Register MSB MISO SPI_TDR TD TDRE 402 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 30.7 Serial Peripheral Interface (SPI) User Interface Register Mapping Register Control Register Mode Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Reserved Reserved for the PDC SPI_CSR0 SPI_CSR1 SPI_CSR2 SPI_CSR3 - Read-write Read-write Read-write Read-write - 0x0 0x0 0x0 0x0 - Name SPI_CR SPI_MR SPI_RDR SPI_TDR SPI_SR SPI_IER SPI_IDR SPI_IMR Access Write-only Read-write Read-only Write-only Read-only Write-only Write-only Read-only Reset --0x0 0x0 --0x000000F0 ----0x0 Table 30-3. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 - 0x2C 0x30 0x34 0x38 0x3C 0x004C - 0x00F8 0x100 - 0x124 403 6384D-ATARM-04-May-09 30.7.1 Name: SPI Control Register SPI_CR Write-only 30 29 28 27 26 25 24 Access Type: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 LASTXFER 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SWRST - - - - - SPIDIS SPIEN * SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. * SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. As soon as SPIDIS is set, SPI finishes its transfer. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. * SWRST: SPI Software Reset 0 = No effect. 1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in slave mode after software reset. PDC channels are not affected by software reset. * LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. 404 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 30.7.2 Name: SPI Mode Register SPI_MR Read/Write 30 29 28 27 26 25 24 Access Type: 31 DLYBCS 23 22 21 20 19 18 17 16 - 15 - 14 - 13 - 12 11 10 PCS 9 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 LLB - - MODFDIS PCSDEC PS MSTR * MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. * PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select. * PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 14. * MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled. * LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.) * PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). 405 6384D-ATARM-04-May-09 If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don't care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. * DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods will be inserted by default. Otherwise, the following equation determines the delay: DLYBCS Delay Between Chip Selects = ---------------------MCK NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected) 406 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 30.7.3 Name: SPI Receive Data Register SPI_RDR Read-only 30 29 28 27 26 25 24 Access Type: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 11 10 PCS 9 8 RD 7 6 5 4 3 2 1 0 RD * RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. * PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. 407 6384D-ATARM-04-May-09 30.7.4 Name: SPI Transmit Data Register SPI_TDR Write-only 30 29 28 27 26 25 24 Access Type: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 LASTXFER 16 - 15 - 14 - 13 - 12 11 10 PCS 9 8 TD 7 6 5 4 3 2 1 0 TD * TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. * PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don't care) If PCSDEC = 1: NPCS[3:0] output signals = PCS * LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. This field is only used if Variable Peripheral Select is active (PS = 1). NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected) 408 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 30.7.5 Name: SPI Status Register SPI_SR Read-only 30 29 28 27 26 25 24 Access Type: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 SPIENS 8 - 7 - 6 - 5 - 4 - 3 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF * RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR. * TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. * MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR. * OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR. * ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). * ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). * RXBUFF: RX Buffer Full 0 = SPI_RCR(1) or SPI_RNCR(1) has a value other than 0. 1 = Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0. 409 6384D-ATARM-04-May-09 * TXBUFE: TX Buffer Empty 0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. * NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. * TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. * SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. Note: 1. SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC. 410 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 30.7.6 Name: SPI Interrupt Enable Register SPI_IER Write-only 30 29 28 27 26 25 24 Access Type: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF * RDRF: Receive Data Register Full Interrupt Enable * TDRE: SPI Transmit Data Register Empty Interrupt Enable * MODF: Mode Fault Error Interrupt Enable * OVRES: Overrun Error Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * ENDTX: End of Transmit Buffer Interrupt Enable * RXBUFF: Receive Buffer Full Interrupt Enable * TXBUFE: Transmit Buffer Empty Interrupt Enable * NSSR: NSS Rising Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. * TXEMPTY: Transmission Registers Empty Enable 411 6384D-ATARM-04-May-09 30.7.7 Name: SPI Interrupt Disable Register SPI_IDR Write-only 30 29 28 27 26 25 24 Access Type: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF * RDRF: Receive Data Register Full Interrupt Disable * TDRE: SPI Transmit Data Register Empty Interrupt Disable * MODF: Mode Fault Error Interrupt Disable * OVRES: Overrun Error Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * ENDTX: End of Transmit Buffer Interrupt Disable * RXBUFF: Receive Buffer Full Interrupt Disable * TXBUFE: Transmit Buffer Empty Interrupt Disable * NSSR: NSS Rising Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. * TXEMPTY: Transmission Registers Empty Disable 412 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 30.7.8 Name: SPI Interrupt Mask Register SPI_IMR Read-only 30 29 28 27 26 25 24 Access Type: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF * RDRF: Receive Data Register Full Interrupt Mask * TDRE: SPI Transmit Data Register Empty Interrupt Mask * MODF: Mode Fault Error Interrupt Mask * OVRES: Overrun Error Interrupt Mask * ENDRX: End of Receive Buffer Interrupt Mask * ENDTX: End of Transmit Buffer Interrupt Mask * RXBUFF: Receive Buffer Full Interrupt Mask * TXBUFE: Transmit Buffer Empty Interrupt Mask * NSSR: NSS Rising Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled. * TXEMPTY: Transmission Registers Empty Mask 413 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 30.7.9 Name: SPI Chip Select Register SPI_CSR0... SPI_CSR3 Read/Write 30 29 28 27 26 25 24 Access Type: 31 DLYBCT 23 22 21 20 19 18 17 16 DLYBS 15 14 13 12 11 10 9 8 SCBR 7 6 5 4 3 2 1 0 BITS CSAAT - NCPHA CPOL * CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. * NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. * CSAAT: Chip Select Active After Transfer 0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. * BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Bits Per Transfer 8 9 10 11 12 13 14 15 16 Reserved Reserved Reserved 414 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary BITS 1100 1101 1110 1111 Bits Per Transfer Reserved Reserved Reserved Reserved * SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: MCK SPCK Baudrate = -------------SCBR Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. * DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: DLYBS Delay Before SPCK = -----------------MCK * DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 x DLYBCT Delay Between Consecutive Transfers = -----------------------------------MCK 415 6384D-ATARM-04-May-09 416 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31. Two-wire Interface (TWI) 31.1 Overview The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and IC compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. Below, Table 31-1 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full I2C compatible device. Table 31-1. I2C Standard Standard Mode Speed (100 KHz) Fast Mode Speed (400 KHz) 7 or 10 bits Slave Addressing START BYTE (1) Atmel TWI compatibility with i2C Standard Atmel TWI Supported Supported Supported Not Supported Supported Supported Not Supported Supported Repeated Start (Sr) Condition ACK and NACK Management Slope control and input filtering (Fast mode) Clock stretching Note: 1. START + b000000001 + Ack + Sr 31.2 List of Abbreviations Table 31-2. Abbreviation TWI A NA P S Sr SADR Abbreviations Description Two-wire Interface Acknowledge Non Acknowledge Stop Start Repeated Start Slave Address 417 6384D-ATARM-04-May-09 Table 31-2. Abbreviation ADR R W Abbreviations Description Any address except SADR Read Write 31.3 Block Diagram Figure 31-1. Block Diagram APB Bridge TWCK PIO Two-wire Interface TWD PMC MCK TWI Interrupt AIC 31.4 Application Block Diagram Figure 31-2. Application Block Diagram VDD Rp TWD TWCK Rp Host with TWI Interface Atmel TWI Serial EEPROM Slave 1 IC RTC Slave 2 IC LCD Controller Slave 3 IC Temp. Sensor Slave 4 Rp: Pull up value as given by the IC Standard 418 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31.4.1 I/O Lines Description I/O Lines Description Pin Description Two-wire Serial Data Two-wire Serial Clock Type Input/Output Input/Output Table 31-3. Pin Name TWD TWCK 31.5 31.5.1 Product Dependencies I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 31-2 on page 418). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following steps: * Program the PIO controller to: - Dedicate TWD and TWCK as peripheral lines. - Define TWD and TWCK as open-drain. 31.5.2 Power Management * Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock. 31.5.3 Interrupt The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI. 31.6 31.6.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 31-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 31-3). * A high-to-low transition on the TWD line while TWCK is high defines the START condition. * A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. 419 6384D-ATARM-04-May-09 Figure 31-3. START and STOP Conditions TWD TWCK Start Stop Figure 31-4. Transfer Format TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop 31.6.2 Modes of Operation The TWI has six modes of operations: * Master transmitter mode * Master receiver mode * Multi-master transmitter mode * Multi-master receiver mode * Slave transmitter mode * Slave receiver mode These modes are described in the following chapters. 420 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31.7 31.7.1 Master Mode Definition The Master is the device that starts a transfer, generates a clock and stops it. 31.7.2 Application Block Diagram Figure 31-5. Master Mode Typical Application Block Diagram VDD Rp TWD TWCK Rp Host with TWI Interface Atmel TWI Serial EEPROM Slave 1 IC RTC Slave 2 IC LCD Controller Slave 3 IC Temp. Sensor Slave 4 Rp: Pull up value as given by the IC Standard 31.7.3 Programming Master Mode The following registers have to be programmed before entering Master mode: 1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave devices in read or write mode. 2. CKDIV + CHDIV + CLDIV: Clock Waveform. 3. SVDIS: Disable the slave mode. 4. MSEN: Enable the master mode. 31.7.4 Master Transmitter Mode After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR). The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR. 421 6384D-ATARM-04-May-09 When no more data is written into the TWI_THR, the master generates a stop condition to end the transfer. The end of the complete transfer is marked by the TWI_TXCOMP bit set to one. See Figure 31-6, Figure 31-7, and Figure 31-8. TXRDY is used as Transmit Ready for the PDC transmit channel. Figure 31-6. Master Write with On Data Byte TWD S DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) STOP sent automaticaly (ACK received and TXRDY = 1) Figure 31-7. Master Write with Multiple Data Byte TWD S DADR W A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x) Last data sent STOP sent automaticaly (ACK received and TXRDY = 1) Figure 31-8. Master Write with One Byte Internal Address and Multiple Data Bytes TWD S DADR W A IADR(7:0) A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x) STOP sent automaticaly Last data sent (ACK received and TXRDY = 1) 31.7.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte. 422 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the master sends an acknowledge condition to notify the slave that the data has been received except for the last data, after the stop condition. See Figure 31-9. When the RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be set at the same time. See Figure 31-9. When a multiple data byte read is performed, with or without internal address (IADR), the STOP bit must be set after the next-tolast data received. See Figure 31-10. For Internal Address usage see Section 31.7.6. Figure 31-9. Master Read with One Data Byte TWD S DADR R A DATA N P TXCOMP Write START & STOP Bit RXRDY Read RHR Figure 31-10. Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read RXRDY is used as Receive Ready for the PDC receive channel. 31.7.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When performing read operations with an internal address, the TWI performs a write operation to set the internal address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is 31.7.6.1 423 6384D-ATARM-04-May-09 sometimes called "repeated start" (Sr) in I2C fully-compatible devices. See Figure 31-12. See Figure 31-11 and Figure 31-13 for Master Write operation with internal address. The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to 0. In the figures below the following abbreviations are used: *S * Sr *P *W *R *A *N * DADR * IADR Start Repeated Start Stop Write Read Acknowledge Not Acknowledge Device Address Internal Address Figure 31-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A DATA A P One byte internal address TWD S DADR W A IADR(7:0) A DATA A P Figure 31-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A Sr DADR R A DATA Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A Sr DADR R A DATA N P N P One byte internal address TWD S DADR W A IADR(7:0) A Sr DADR R A DATA N P 31.7.6.2 10-bit Slave Addressing For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). The two remaining 424 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave Addressing. Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.) 3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address) Figure 31-13 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 31-13. Internal Address Usage S T A R T W R I T E S T O P Device Address 0 M S B FIRST WORD ADDRESS SECOND WORD ADDRESS DATA LRA S/C BW K M S B A C K LA SC BK A C K 425 6384D-ATARM-04-May-09 31.7.7 Using the Peripheral DMA Controller (PDC) The use of the PDC significantly reduces the CPU load. To assure correct implementation, respect the following programming sequences: 31.7.7.1 Data Transmit with the PDC 1. Initialize the transmit PDC (memory pointers, size, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC TXTEN bit. 4. Wait for the PDC end TX flag. 5. Disable the PDC by setting the PDC TXDIS bit. 31.7.7.2 Data Receive with the PDC 1. Initialize the receive PDC (memory pointers, size - 1, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC RXTEN bit. 4. Wait for the PDC end RX flag. 5. Disable the PDC by setting the PDC RXDIS bit. 31.7.8 Read-write Flowcharts The following flowcharts shown in Figure 31-15 on page 428, Figure 31-16 on page 429, Figure 31-17 on page 430, Figure 31-18 on page 431 and Figure 31-19 on page 432 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. 426 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 31-14. TWI Write Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Transfer direction bit Write ==> bit MREAD = 0 Load Transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status register No TXCOMP = 1? Yes Transfer finished 427 6384D-ATARM-04-May-09 Figure 31-15. TWI Write Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Set the internal address TWI_IADR = address Load transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status register TXCOMP = 1? No Yes Transfer finished 428 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 31-16. TWI Write Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 No Internal address size = 0? Set the internal address TWI_IADR = address Yes Load Transmit register TWI_THR = Data to send Read Status register TWI_THR = data to send TXRDY = 1? Yes Data to send? Yes No Read Status register Yes No TXCOMP = 1? END 429 6384D-ATARM-04-May-09 Figure 31-17. TWI Read Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWI_CR = START | STOP Read status register RXRDY = 1? Yes Read Receive Holding Register No Read Status register No TXCOMP = 1? Yes END 430 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 31-18. TWI Read Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Set the internal address TWI_IADR = address Start the transfer TWI_CR = START | STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register Read Status register No TXCOMP = 1? Yes END 431 6384D-ATARM-04-May-09 Figure 31-19. TWI Read Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 Internal address size = 0? Set the internal address TWI_IADR = address Yes Start the transfer TWI_CR = START Read Status register RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) No No Last data to read but one? Yes Stop the transfer TWI_CR = STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) Read status register TXCOMP = 1? Yes END No 432 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31.8 31.8.1 Multi-master Mode Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. Arbitration is illustrated in Figure 31-21 on page 434. 31.8.2 Different Multi-master Modes Two multi-master modes may be distinguished: 1. TWI is considered as a Master only and will never be addressed. 2. TWI may be either a Master or a Slave and may be addressed. Note: In both Multi-master modes arbitration is supported. 31.8.2.1 TWI as Master Only In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with the ARBLST (ARBitration Lost) flag in addition. If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer. If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically waits for a STOP condition on the bus to initiate the transfer (see Figure 3120 on page 434). Note: The state of the bus (busy or free) is not indicated in the user interface. 31.8.2.2 TWI as Master or Slave The automatic reversal from Master to Slave is not supported in case of a lost arbitration. Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-master mode described in the steps below. 1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if TWI is addressed). 2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1. 3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR). 4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the bus is considered as free, TWI initiates the transfer. 5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag. 6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case where the Master that won the arbitration wanted to access the TWI. 7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode. 433 6384D-ATARM-04-May-09 Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR. Figure 31-20. Programmer Sends Data While the Bus is Busy TWCK STOP sent by the master TWD DATA sent by a master Bus is busy Bus is free TWI DATA transfer Transfer is kept START sent by the TWI DATA sent by the TWI A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 31-21. Arbitration Cases TWCK TWD TWCK Data from a Master Data from TWI TWD S S S 1 1 1 0 0 11 0 1 Arbitration is lost TWI stops sending data P S S 1 1 1 0 1 Arbitration is lost The master stops sending data 0 01 0 01 1 1 Data from the TWI 00 11 Data from the master P S ARBLST Bus is busy Bus is free TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Transfer is stopped Transfer is kept Transfer is programmed again (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated The flowchart shown in Figure 31-22 on page 435 gives an example of read and write operations in Multi-master mode. 434 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 31-22. Multi-master Flowchart START Programm the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? No No EOSACC = 1 ? Yes No TXCOMP = 1 ? Yes No Yes GACC = 1 ? No No No SVREAD = 0 ? Yes TXRDY= 1 ? Yes Write in TWI_THR RXRDY= 0 ? Yes Read TWI_RHR No Need to perform a master access ? GENERAL CALL TREATMENT Yes Decoding of the programming sequence Prog seq OK ? Change SADR Program the Master mode DADR + SVDIS + MSEN + CLK + R / W No Read Status Register Yes ARBLST = 1 ? No Yes Yes MREAD = 1 ? No Yes RXRDY= 0 ? No TXRDY= 0 ? No Data to send ? No Stop transfer Read TWI_RHR Yes Data to read? No Yes Write in TWI_THR Read Status Register Yes No TXCOMP = 0 ? 435 6384D-ATARM-04-May-09 31.9 31.9.1 Slave Mode Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 31.9.2 Application Block Diagram Figure 31-23. Slave Mode Typical Application Block Diagram VDD R TWD TWCK R Master Host with TWI Interface Host with TWI Interface Slave 1 Host with TWI Interface Slave 2 LCD Controller Slave 3 31.9.3 Programming Slave Mode The following fields must be programmed before entering Slave mode: 1. SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write mode. 2. MSDIS (TWI_CR): Disable the master mode. 3. SVEN (TWI_CR): Enable the slave mode. As the device receives the clock, values written in TWI_CWGR are not taken into account. 31.9.4 Receiving Data After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer. SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected, EOSACC (End Of Slave ACCess) flag is set. 31.9.4.1 Read Sequence In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit Holding Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset. As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set. 436 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Note that a STOP or a repeated START always follows a NACK. See Figure 31-24 on page 438. 31.9.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 31-25 on page 438. 31.9.4.3 Clock Synchronization Sequence In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization. Clock stretching information is given by the SCLWS (Clock Wait state) bit. See Figure 31-27 on page 440 and Figure 31-28 on page 441. 31.9.4.4 General Call In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set. After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence. See Figure 31-26 on page 439. 31.9.4.5 PDC As it is impossible to know the exact number of data to receive/send, the use of PDC is NOT recommended in SLAVE mode. 31.9.5 31.9.5.1 Data Transfer Read Operation The read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer. Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 31-24 on page 438 describes the write operation. 437 6384D-ATARM-04-May-09 Figure 31-24. Read Access Ordered by a MASTER SADR does not match, TWI answers with a NACK SADR matches, TWI answers with an ACK ACK/NACK from the Master A DATA NA S/Sr TWD TXRDY NACK SVACC SVREAD EOSVACC S ADR R NA DATA NA P/S/Sr SADR R A DATA A Write THR Read RHR SVREAD has to be taken into account only while SVACC is active Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. 31.9.5.2 Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 31-25 on page 438 describes the Write operation. Figure 31-25. Write Access Ordered by a Master SADR does not match, TWI answers with a NACK SADR matches, TWI answers with an ACK Read RHR TWD RXRDY SVACC SVREAD EOSVACC Notes: S ADR W NA DATA NA P/S/Sr SADR W A DATA A A DATA NA S/Sr SVREAD has to be taken into account only while SVACC is active 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read. 438 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31.9.5.3 General Call The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of General Call, it is up to the programmer to decode the commands which come afterwards. In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches. Figure 31-26 on page 439 describes the General Call access. Figure 31-26. Master Performs a General Call 0000000 + W RESET command = 00000110X WRITE command = 00000100X A TXD S GENERAL CALL A Reset or write DADD A DATA1 A DATA2 A New SADR P New SADR Programming sequence GCACC Reset after read SVACC Note: This method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master. 439 6384D-ATARM-04-May-09 31.9.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded. Figure 31-27 on page 440 describes the clock synchronization in Read mode. 31.9.5.5 Figure 31-27. Clock Synchronization in Read Mode TWI_THR DATA0 1 DATA1 DATA2 S SADR R A DATA0 A DATA1 A XXXXXXX 2 DATA2 NA S TWCK Write THR CLOCK is tied low by the TWI as long as THR is empty SCLWS TXRDY SVACC SVREAD TXCOMP As soon as a START is detected TWI_THR is transmitted to the shift register 1 2 The data is memorized in TWI_THR until a new value is written Ack or Nack from the master The clock is stretched after the ACK, the state of TWD is undefined during clock stretching Notes: 1. TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. 2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 3. SCLWS is automatically set when the clock synchronization mechanism is started. 440 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31.9.5.6 Clock Synchronization in Write Mode The c lock is tied lo w if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 31-28 on page 441 describes the clock synchronization in Read mode. Figure 31-28. Clock Synchronization in Write Mode TWCK CLOCK is tied low by the TWI as long as RHR is full TWD S SADR W A DATA0 A DATA1 A DATA2 NA S ADR TWI_RHR SCLWS DATA0 is not read in the RHR DATA1 DATA2 SCL is stretched on the last bit of DATA1 RXRDY Rd DATA0 SVACC SVREAD TXCOMP As soon as a START is detected Rd DATA1 Rd DATA2 Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished. 441 6384D-ATARM-04-May-09 31.9.5.7 31.9.5.8 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 31-29 on page 442 describes the repeated start + reversal from Read to Write mode. Figure 31-29. Repeated Start + Reversal from Read to Write Mode TWI_THR DATA0 DATA1 TWD S SADR R A DATA0 A DATA1 NA Sr SADR W A DATA2 A DATA3 A DATA3 P TWI_RHR SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP As soon as a START is detected DATA2 Cleared after read 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. 31.9.5.9 Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command.Figure 31-30 on page 442 describes the repeated start + reversal from Write to Read mode. Figure 31-30. Repeated Start + Reversal from Write to Read Mode TWI_THR DATA2 DATA3 TWD TWI_RHR SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP S SADR W A DATA0 A DATA1 A Sr SADR R A DATA2 A DATA3 NA P DATA0 DATA1 Read TWI_RHR As soon as a START is detected Cleared after read Notes: 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK. 2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. 442 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31.9.6 Read Write Flowcharts The flowchart shown in Figure 31-31 on page 443 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 31-31. Read Write Flowchart in Slave Mode Set the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? No No GACC = 1 ? No SVREAD = 0 ? No EOSACC = 1 ? TXRDY= 1 ? No No Write in TWI_THR TXCOMP = 1 ? RXRDY= 0 ? END Read TWI_RHR No GENERAL CALL TREATMENT Decoding of the programming sequence Prog seq OK ? No Change SADR 443 6384D-ATARM-04-May-09 31.10 Two-wire Interface (TWI) User Interface Table 31-4. Offset 0x00 0x04 0x08 0x0C 0x10 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 - 0xFC 0x100 - 0x124 Register Mapping Register Control Register Master Mode Register Slave Mode Register Internal Address Register Clock Waveform Generator Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Receive Holding Register Transmit Holding Register Reserved Reserved for the PDC Name TWI_CR TWI_MMR TWI_SMR TWI_IADR TWI_CWGR TWI_SR TWI_IER TWI_IDR TWI_IMR TWI_RHR TWI_THR - - Access Write-only Read-write Read-write Read-write Read-write Read-only Write-only Write-only Read-only Read-only Write-only - - Reset N/A 0x00000000 0x00000000 0x00000000 0x00000000 0x0000F009 N/A N/A 0x00000000 0x00000000 0x00000000 - - 444 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31.10.1 Name: Access: TWI Control Register TWI_CR Write-only Reset Value: 0x00000000 31 - 23 - 15 - 7 SWRST 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 SVDIS 28 - 20 - 12 - 4 SVEN 27 - 19 - 11 - 3 MSDIS 26 - 18 - 10 - 2 MSEN 25 - 17 - 9 - 1 STOP 24 - 16 - 8 - 0 START * START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR). * STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read mode. - In single data byte master read, the START and STOP must both be set. - In multiple data bytes master read, the STOP must be set after the last data received but one. - In master read mode, if a NACK bit is received, the STOP is automatically performed. - In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent. * MSEN: TWI Master Mode Enabled 0 = No effect. 1 = If MSDIS = 0, the master mode is enabled. Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1. * MSDIS: TWI Master Mode Disabled 0 = No effect. 1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. 445 6384D-ATARM-04-May-09 * SVEN: TWI Slave Mode Enabled 0 = No effect. 1 = If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. * SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. * SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset. 446 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31.10.2 Name: Access: TWI Master Mode Register TWI_MMR Read-write Reset Value: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 29 - 21 28 - 20 27 - 19 DADR 11 - 3 - 26 - 18 25 - 17 24 - 16 14 - 6 - 13 - 5 - 12 MREAD 4 - 10 - 2 - 9 IADRSZ 1 - 8 0 - * IADRSZ: Internal Device Address Size IADRSZ[9:8] 0 0 1 1 0 1 0 1 No internal device address One-byte internal device address Two-byte internal device address Three-byte internal device address * MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction. * DADR: Device Address The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode. 447 6384D-ATARM-04-May-09 31.10.3 Name: Access: TWI Slave Mode Register TWI_SMR Read-write Reset Value: 0x00000000 31 - 23 - 15 - 7 - 30 - 22 29 - 21 28 - 20 27 - 19 SADR 11 - 3 - 26 - 18 25 - 17 24 - 16 14 - 6 - 13 - 5 - 12 - 4 - 10 - 2 - 9 8 1 - 0 - * SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect. 31.10.4 Name: Access: TWI Internal Address Register TWI_IADR Read-write Reset Value: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 IADR 15 14 13 12 IADR 7 6 5 4 IADR 3 2 1 0 11 10 9 8 27 - 19 26 - 18 25 - 17 24 - 16 * IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. 448 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31.10.5 Name: Access: TWI Clock Waveform Generator Register TWI_CWGR Read-write Reset Value: 0x00000000 31 - 23 30 - 22 29 - 21 28 - 20 27 - 19 26 - 18 25 - 17 CKDIV 9 24 - 16 15 14 13 12 CHDIV 11 10 8 7 6 5 4 CLDIV 3 2 1 0 TWI_CWGR is only used in Master mode. * CLDIV: Clock Low Divider The SCL low period is defined as follows: T low = ( ( CLDIV x 2 CKDIV ) + 4 ) x T MCK * CHDIV: Clock High Divider The SCL high period is defined as follows: T high = ( ( CHDIV x 2 CKDIV ) + 4 ) x T MCK * CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods. 449 6384D-ATARM-04-May-09 31.10.6 Name: Access: TWI Status Register TWI_SR Read-only Reset Value: 0x0000F009 31 - 23 - 15 TXBUFE 7 - 30 - 22 - 14 RXBUFF 6 OVRE 29 - 21 - 13 ENDTX 5 GACC 28 - 20 - 12 ENDRX 4 SVACC 27 - 19 - 11 EOSACC 3 SVREAD 26 - 18 - 10 SCLWS 2 TXRDY 25 - 17 - 9 ARBLST 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP * TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame. 1 = When both holding and shifter registers are empty and STOP condition has been sent. TXCOMP behavior in Master mode can be seen in Figure 31-7 on page 422 and in Figure 31-10 on page 423. TXCOMP used in Slave mode: 0 = As soon as a Start is detected. 1 = After a Stop or a Repeated Start + an address different from SADR is detected. TXCOMP behavior in Slave mode can be seen in Figure 31-27 on page 440, Figure 31-28 on page 441, Figure 31-29 on page 442 and Figure 31-30 on page 442. * RXRDY: Receive Holding Register Ready (automatically set / reset) 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in the TWI_RHR since the last read. RXRDY behavior in Master mode can be seen in Figure 31-10 on page 423. RXRDY behavior in Slave mode can be seen in Figure 31-25 on page 438, Figure 31-28 on page 441, Figure 31-29 on page 442 and Figure 31-30 on page 442. * TXRDY: Transmit Holding Register Ready (automatically set / reset) TXRDY used in Master mode: 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). TXRDY behavior in Master mode can be seen in Figure 31-8 on page 422. 450 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary TXRDY used in Slave mode: 0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 31-24 on page 438, Figure 31-27 on page 440, Figure 31-29 on page 442 and Figure 31-30 on page 442. * SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant. 0 = Indicates that a write access is performed by a Master. 1 = Indicates that a read access is performed by a Master. SVREAD behavior can be seen in Figure 31-24 on page 438, Figure 31-25 on page 438, Figure 31-29 on page 442 and Figure 31-30 on page 442. * SVACC: Slave Access (automatically set / reset) This bit is only used in Slave mode. 0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. SVACC behavior can be seen in Figure 31-24 on page 438, Figure 31-25 on page 438, Figure 31-29 on page 442 and Figure 31-30 on page 442. * GACC: General Call Access (clear on read) This bit is only used in Slave mode. 0 = No General Call has been detected. 1 = A General Call has been detected. After the detection of General Call, the programmer decoded the commands that follow and the programming sequence. GACC behavior can be seen in Figure 31-26 on page 439. * OVRE: Overrun Error (clear on read) This bit is only used in Master mode. 0 = TWI_RHR has not been loaded while RXRDY was set 1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. * NACK: Not Acknowledged (clear on read) NACK used in Master mode: 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. 451 6384D-ATARM-04-May-09 NACK used in Slave Read mode: 0 = Each data byte has been correctly received by the Master. 1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI. * ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. * SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0 = The clock is not stretched. 1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. SCLWS behavior can be seen in Figure 31-27 on page 440 and Figure 31-28 on page 441. * EOSACC: End Of Slave Access (clear on read) This bit is only used in Slave mode. 0 = A slave access is being performing. 1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. EOSACC behavior can be seen in Figure 31-29 on page 442 and Figure 31-30 on page 442 * ENDRX: End of RX buffer This bit is only used in Master mode. 0 = The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR. * ENDTX: End of TX buffer This bit is only used in Master mode. 0 = The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR. * RXBUFF: RX Buffer Full This bit is only used in Master mode. 0 = TWI_RCR or TWI_RNCR have a value other than 0. 1 = Both TWI_RCR and TWI_RNCR have a value of 0. 452 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * TXBUFE: TX Buffer Empty This bit is only used in Master mode. 0 = TWI_TCR or TWI_TNCR have a value other than 0. 1 = Both TWI_TCR and TWI_TNCR have a value of 0. 453 6384D-ATARM-04-May-09 31.10.7 Name: Access: TWI Interrupt Enable Register TWI_IER Write-only Reset Value: 0x00000000 31 - 23 - 15 TXBUFE 7 - 30 - 22 - 14 RXBUFF 6 OVRE 29 - 21 - 13 ENDTX 5 GACC 28 - 20 - 12 ENDRX 4 SVACC 27 - 19 - 11 EOSACC 3 - 26 - 18 - 10 SCL_WS 2 TXRDY 25 - 17 - 9 ARBLST 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP * TXCOMP: Transmission Completed Interrupt Enable * RXRDY: Receive Holding Register Ready Interrupt Enable * TXRDY: Transmit Holding Register Ready Interrupt Enable * SVACC: Slave Access Interrupt Enable * GACC: General Call Access Interrupt Enable * OVRE: Overrun Error Interrupt Enable * NACK: Not Acknowledge Interrupt Enable * ARBLST: Arbitration Lost Interrupt Enable * SCL_WS: Clock Wait State Interrupt Enable * EOSACC: End Of Slave Access Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * ENDTX: End of Transmit Buffer Interrupt Enable * RXBUFF: Receive Buffer Full Interrupt Enable * TXBUFE: Transmit Buffer Empty Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 454 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31.10.8 Name: Access: TWI Interrupt Disable Register TWI_IDR Write-only Reset Value: 0x00000000 31 - 23 - 15 TXBUFE 7 - 30 - 22 - 14 RXBUFF 6 OVRE 29 - 21 - 13 ENDTX 5 GACC 28 - 20 - 12 ENDRX 4 SVACC 27 - 19 - 11 EOSACC 3 - 26 - 18 - 10 SCL_WS 2 TXRDY 25 - 17 - 9 ARBLST 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP * TXCOMP: Transmission Completed Interrupt Disable * RXRDY: Receive Holding Register Ready Interrupt Disable * TXRDY: Transmit Holding Register Ready Interrupt Disable * SVACC: Slave Access Interrupt Disable * GACC: General Call Access Interrupt Disable * OVRE: Overrun Error Interrupt Disable * NACK: Not Acknowledge Interrupt Disable * ARBLST: Arbitration Lost Interrupt Disable * SCL_WS: Clock Wait State Interrupt Disable * EOSACC: End Of Slave Access Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * ENDTX: End of Transmit Buffer Interrupt Disable * RXBUFF: Receive Buffer Full Interrupt Disable * TXBUFE: Transmit Buffer Empty Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 455 6384D-ATARM-04-May-09 31.10.9 Name: Access: TWI Interrupt Mask Register TWI_IMR Read-only Reset Value: 0x00000000 31 - 23 - 15 TXBUFE 7 - 30 - 22 - 14 RXBUFF 6 OVRE 29 - 21 - 13 ENDTX 5 GACC 28 - 20 - 12 ENDRX 4 SVACC 27 - 19 - 11 EOSACC 3 - 26 - 18 - 10 SCL_WS 2 TXRDY 25 - 17 - 9 ARBLST 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP * TXCOMP: Transmission Completed Interrupt Mask * RXRDY: Receive Holding Register Ready Interrupt Mask * TXRDY: Transmit Holding Register Ready Interrupt Mask * SVACC: Slave Access Interrupt Mask * GACC: General Call Access Interrupt Mask * OVRE: Overrun Error Interrupt Mask * NACK: Not Acknowledge Interrupt Mask * ARBLST: Arbitration Lost Interrupt Mask * SCL_WS: Clock Wait State Interrupt Mask * EOSACC: End Of Slave Access Interrupt Mask * ENDRX: End of Receive Buffer Interrupt Mask * ENDTX: End of Transmit Buffer Interrupt Mask * RXBUFF: Receive Buffer Full Interrupt Mask * TXBUFE: Transmit Buffer Empty Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 456 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31.10.10 TWI Receive Holding Register Name: TWI_RHR Access: Read-only Reset Value: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RXDATA 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * RXDATA: Master or Slave Receive Holding Data 457 6384D-ATARM-04-May-09 31.10.11 TWI Transmit Holding Register Name: TWI_THR Access: Read-write Reset Value: 0x00000000 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TXDATA 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * TXDATA: Master or Slave Transmit Holding Data 458 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32. Universal Synchronous Asynchronous Receiver Transmitter (USART) 32.1 Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor. 459 6384D-ATARM-04-May-09 32.2 Block Diagram Figure 32-1. USART Block Diagram Peripheral DMA Controller Channel Channel USART PIO Controller RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS DTR PMC MCK MCK/DIV Modem Signals Control DSR DCD RI SLCK Baud Rate Generator SCK DIV User Interface APB 460 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.3 Application Block Diagram Figure 32-2. Application Block Diagram PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrLAP IrDA Driver USART RS232 Drivers Modem PSTN RS232 Drivers RS485 Drivers Smart Card Slot IrDA Transceivers Serial Port Differential Bus 461 6384D-ATARM-04-May-09 32.4 I/O Lines Description I/O Line Description Description Serial Clock Transmit Serial Data Receive Serial Data Ring Indicator Data Set Ready Data Carrier Detect Data Terminal Ready Clear to Send Request to Send Type I/O I/O Input Input Input Input Output Input Output Low Low Low Low Low Low Active Level Table 32-1. Name SCK TXD RXD RI DSR DCD DTR CTS RTS 462 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.5 32.5.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the hardware handshaking feature or Modem mode is used, the internal pull up on TXD must also be enabled. All the pins of the modems may or may not be implemented on the USART. Only USART0 is fully equipped with all the modem signals. On USARTs not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the USART. 32.5.2 Power Management The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled. 32.5.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. 463 6384D-ATARM-04-May-09 32.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: * 5- to 9-bit full-duplex asynchronous serial communication - MSB- or LSB-first - 1, 1.5 or 2 stop bits - Parity even, odd, marked, space or none - By 8 or by 16 over-sampling receiver frequency - Optional hardware handshaking - Optional modem signals management - Optional break management - Optional multidrop serial communication * High-speed 5- to 9-bit full-duplex synchronous serial communication - MSB- or LSB-first - 1 or 2 stop bits - Parity even, odd, marked, space or none - By 8 or by 16 over-sampling frequency - Optional hardware handshaking - Optional modem signals management - Optional break management - Optional multidrop serial communication * RS485 with driver control signal * ISO7816, T0 or T1 protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit * InfraRed IrDA Modulation and Demodulation * Test modes - Remote loopback, local loopback, automatic echo 32.6.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between: * the Master Clock MCK * a division of the Master Clock, the divider being product dependent, but generally set to 8 * the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. 464 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. Figure 32-3. Baud Rate Generator USCLKS MCK MCK/DIV SCK Reserved CD CD 0 1 2 3 0 16-bit Counter >1 1 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 OVER Sampling Divider 0 Baud Rate Clock FIDI SYNC SCK 32.6.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate. SelectedClock Baudrate = -------------------------------------------( 8 ( 2 - Over )CD ) This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1. 32.6.1.2 Baud Rate Calculation Example Table 32-2 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Baud Rate Example (OVER = 0) Expected Baud Rate Bit/s 38 400 38 400 38 400 38 400 6.00 8.00 8.14 12.00 6 8 8 12 Calculation Result CD Actual Baud Rate Bit/s 38 400.00 38 400.00 39 062.50 38 400.00 0.00% 0.00% 1.70% 0.00% Error Table 32-2. Source Clock MHz 3 686 400 4 915 200 5 000 000 7 372 800 465 6384D-ATARM-04-May-09 Table 32-2. Baud Rate Example (OVER = 0) (Continued) Expected Baud Rate 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 Calculation Result 13.02 19.53 20.00 23.30 24.00 30.00 39.06 40.00 40.69 52.08 53.33 53.71 65.10 81.38 CD 13 20 20 23 24 30 39 40 40 52 53 54 65 81 Actual Baud Rate 38 461.54 37 500.00 38 400.00 38 908.10 38 400.00 38 400.00 38 461.54 38 400.00 38 109.76 38 461.54 38 641.51 38 194.44 38 461.54 38 580.25 Error 0.16% 2.40% 0.00% 1.31% 0.00% 0.00% 0.16% 0.00% 0.76% 0.16% 0.63% 0.54% 0.16% 0.47% Source Clock 8 000 000 12 000 000 12 288 000 14 318 180 14 745 600 18 432 000 24 000 000 24 576 000 25 000 000 32 000 000 32 768 000 33 000 000 40 000 000 50 000 000 The baud rate is calculated with the following formula: BaudRate = MCK CD x 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. ExpectedBaudRate Error = 1 - -------------------------------------------------- ActualBaudRate 32.6.1.3 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: SelectedClock Baudrate = --------------------------------------------------------------- 8 ( 2 - Over ) CD + FP ----- 8 The modified architecture is presented below: 466 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 32-4. Fractional Baud Rate Generator FP USCLKS MCK MCK/DIV SCK Reserved CD Modulus Control FP CD SCK FIDI 0 OVER Sampling Divider 1 1 SYNC USCLKS = 3 Sampling Clock 0 Baud Rate Clock SYNC 0 1 2 3 16-bit Counter glitch-free logic >1 1 0 0 32.6.1.4 Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. BaudRate = SelectedClock ------------------------------------CD In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. 32.6.1.5 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ----- x f Fi where: * B is the bit rate * Di is the bit-rate adjustment factor * Fi is the clock frequency division factor * f is the ISO7816 clock frequency (Hz) 467 6384D-ATARM-04-May-09 Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 32-3. Table 32-3. DI field Di (decimal) Binary and Decimal Values for Di 0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20 Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 32-4. Table 32-4. FI field Fi (decimal Binary and Decimal Values for Fi 0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048 Table 32-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 32-5. Fi/Di 1 2 4 8 16 32 12 20 Possible Values for the Fi/Di Ratio 372 372 186 93 46.5 23.25 11.62 31 18.6 558 558 279 139.5 69.75 34.87 17.43 46.5 27.9 774 744 372 186 93 46.5 23.25 62 37.2 1116 1116 558 279 139.5 69.75 34.87 93 55.8 1488 1488 744 372 186 93 46.5 124 74.4 1806 1860 930 465 232.5 116.2 58.13 155 93 512 512 256 128 64 32 16 42.66 25.6 768 768 384 192 96 48 24 64 38.4 1024 1024 512 256 128 64 32 85.33 51.2 1536 1536 768 384 192 96 48 128 76.8 2048 2048 1024 512 256 128 64 170.6 102.4 If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 32-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. 468 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 32-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 32.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally. 32.6.3 32.6.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only. 469 6384D-ATARM-04-May-09 Figure 32-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. Figure 32-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 32.6.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. Figure 32-8 illustrates this coding scheme. 470 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 32-8. NRZ to Manchester Encoding NRZ encoded data Manchester encoded data 1 0 1 1 0 0 0 1 Txd The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the field TX_PL is used to configure the preamble length. Figure 32-9 illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. Figure 32-9. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT field in the US_MR register. It consists of a user-defined pattern that indicates the beginning of a valid data. Figure 32-10 illustrates these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT at 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT at 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new 471 6384D-ATARM-04-May-09 character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in the US_MR register is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a modified character located in memory. To enable this mode, VAR_SYNC field in US_MR register must be set to 1. In this case, the MODSYNC field in US_MR is bypassed and the sync configuration is held in the TXSYNH in the US_THR register. The USART character format is modified and includes sync information. Figure 32-10. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data Txd DATA One bit start frame delimiter SFD Manchester encoded data Txd DATA SFD Manchester encoded data Txd Command Sync start frame delimiter DATA Data Sync start frame delimiter 32.6.3.3 Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken. 472 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 32-11. Bit Resynchronization Oversampling 16x Clock RXD Sampling point Expected edge Synchro. Error Synchro. Jump Tolerance Sync Jump Synchro. Error 32.6.3.4 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 32-12 and Figure 32-13 illustrate start detection and character reception when USART operates in asynchronous mode. 473 6384D-ATARM-04-May-09 Figure 32-12. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 01 Start Rejection 7 2 3 4 Figure 32-13. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 32.6.3.5 Manchester Decoder When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in US_MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP field in US_MAN. See Figure 32-9 for available preamble patterns. Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time at zero, a start bit is detected. See Figure 32-14.. The sample pulse rejection mechanism applies. 474 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 32-14. Asynchronous Start Bit Detection Sampling Clock (16 x) Manchester encoded data Txd Start Detection 1 2 3 4 The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time. If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into NRZ data and passed to USART for processing. Figure 32-15 illustrates Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, MANE flag in US_CSR register is raised. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. See Figure 32-16 for an example of Manchester error detection during data phase. Figure 32-15. Preamble Pattern Mismatch Preamble Mismatch Manchester coding error Preamble Mismatch invalid pattern Manchester encoded data Txd SFD DATA Preamble Length is set to 8 Figure 32-16. Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded Manchester Coding Error detected 475 6384D-ATARM-04-May-09 When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. As the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-toone transition. 32.6.3.6 Radio Interface: Manchester Encoded USART Application This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes. The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the configuration in Figure 32-17. Figure 32-17. Manchester Encoded Characters RF Transmission Fup frequency Carrier ASK/FSK Upstream Receiver Upstream Emitter LNA VCO RF filter Demod Serial Configuration Interface control Fdown frequency Carrier bi-dir line ASK/FSK downstream transmitter Manchester decoder USART Receiver Downstream Receiver Manchester encoder PA RF filter Mod VCO USART Emitter control The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 32-18 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 32-19. 476 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver switches to receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration. Figure 32-18. ASK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output ASK Modulator Output Uptstream Frequency F0 0 0 1 Txd Figure 32-19. FSK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 0 0 1 Txd 32.6.3.7 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 32-20 illustrates a character reception in synchronous mode. 477 6384D-ATARM-04-May-09 Figure 32-20. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 32.6.3.8 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1. Figure 32-21. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 478 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.6.3.9 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see "Multidrop Mode" on page 480. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 32-6 shows an example of the parity bit for the character 0x41 (character ASCII "A") depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 32-6. Character A A A A A Parity Bit Examples Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 32-22 illustrates the parity bit status setting and clearing. 479 6384D-ATARM-04-May-09 Figure 32-22. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 32.6.3.10 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0. 32.6.3.11 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 32-23, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. 480 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 32-23. Timeguard Operations TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit TG = 4 Write US_THR TXRDY TXEMPTY Table 32-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 32-7. Maximum Timeguard Length Depending on Baud Rate Bit time s 833 104 69.4 52.1 34.7 29.9 17.9 17.4 8.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 7.63 4.55 4.43 2.21 Baud Rate Bit/sec 1 200 9 600 14400 19200 28800 33400 56000 57600 115200 32.6.3.12 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either: * Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state 481 6384D-ATARM-04-May-09 on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. * Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 32-24 shows the block diagram of the Receiver Time-out feature. Figure 32-24. Receiver Time-out Block Diagram Baud Rate Clock TO 1 STTTO D Q Clock 16-bit Time-out Counter Load 16-bit Value = TIMEOUT Character Received RETTO Clear 0 Table 32-8 gives the maximum time-out period for some standard baud rates. Table 32-8. Maximum Time-out Period Bit Time s 1 667 833 417 208 104 69 52 35 30 Time-out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962 Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400 482 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 32-8. Maximum Time-out Period (Continued) Bit Time 18 17 5 Time-out 1 170 1 138 328 Baud Rate 56000 57600 200000 32.6.3.13 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 32-25. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 32.6.3.14 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 483 6384D-ATARM-04-May-09 The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 32-26 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 32-26. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Break Transmission STPBRK = 1 End of Break STTBRK = 1 Write US_CR TXRDY TXEMPTY 32.6.3.15 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. 32.6.3.16 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 32-27. 484 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 32-27. Connection with a Remote Device for Hardware Handshaking USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 32-28 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 32-28. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 Write US_CR RTS RXBUFF RXDIS = 1 Figure 32-29 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 32-29. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 485 6384D-ATARM-04-May-09 32.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 32.6.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see "Baud Rate Generator" on page 464). The USART connects to a smart card as shown in Figure 32-30. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 32-30. Connection of a Smart Card to the USART USART SCK TXD CLK I/O Smart Card When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to "USART Mode Register" on page 499 and "PAR: Parity Type" on page 500. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR). 32.6.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 32-31. 486 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 32-32. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 32-31. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 32-32. T = 0 Protocol with Parity Error Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition 32.6.4.3 Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. 32.6.4.4 32.6.4.5 Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. 487 6384D-ATARM-04-May-09 When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1. 32.6.4.6 Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 32-33. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 32-33. Connection to IrDA Transceivers 32.6.4.7 32.6.5 USART Receiver Demodulator RXD RX TX Transmitter Modulator TXD IrDA Transceivers The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done: * Disable TX and Enable RX 488 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * Configure the TXD pin as PIO and set it as an output at 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption). * Receive data 32.6.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. "0" is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 32-9. Table 32-9. Baud Rate 2.4 Kb/s 9.6 Kb/s 19.2 Kb/s 38.4 Kb/s 57.6 Kb/s 115.2 Kb/s IrDA Pulse Duration Pulse Duration (3/16) 78.13 s 19.53 s 9.77 s 4.88 s 3.26 s 1.63 s Figure 32-34 shows an example of character transmission. Figure 32-34. IrDA Modulation Start Bit Transmitter Output 0 1 0 1 Data Bits 0 0 1 1 0 Stop Bit 1 TXD Bit Period 3 16 Bit Period 32.6.5.2 IrDA Baud Rate Table 32-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of 1.87% must be met. Table 32-10. IrDA Baud Rate Error Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 115 200 115 200 115 200 115 200 57 600 57 600 57 600 CD 2 11 18 22 4 22 36 Baud Rate Error 0.00% 1.38% 1.25% 1.38% 0.00% 1.38% 1.25% Pulse Time 1.63 1.63 1.63 1.63 3.26 3.26 3.26 489 6384D-ATARM-04-May-09 Table 32-10. IrDA Baud Rate Error (Continued) Peripheral Clock 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 57 600 38 400 38 400 38 400 38 400 19 200 19 200 19 200 19 200 9 600 9 600 9 600 9 600 2 400 2 400 2 400 CD 43 6 33 53 65 12 65 107 130 24 130 213 260 96 521 853 Baud Rate Error 0.93% 0.00% 1.38% 0.63% 0.16% 0.00% 0.16% 0.31% 0.16% 0.00% 0.16% 0.16% 0.16% 0.00% 0.03% 0.04% Pulse Time 3.26 4.88 4.88 4.88 4.88 9.77 9.77 9.77 9.77 19.53 19.53 19.53 19.53 78.13 78.13 78.13 32.6.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 32-35 illustrates the operations of the IrDA demodulator. Figure 32-35. IrDA Demodulator Operations MCK RXD Counter Value 6 Receiver Input 43 Pulse Rejected 5 2 6 6 5 4 3 2 1 0 Pulse Accepted As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 490 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 32-36. Figure 32-36. Typical Connection to a RS485 Bus USART RXD TXD RTS Differential Bus The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 32-37 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 32-37. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 491 6384D-ATARM-04-May-09 32.6.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in modem mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the parameter configurations are available. Table 32-11 gives the correspondence of the USART signals with modem connection standards. Table 32-11. Circuit References USART Pin TXD RTS DTR RXD CTS DSR DCD RI V24 2 4 20 3 5 6 8 22 CCITT 103 105 108.2 104 106 107 109 125 Direction From terminal to modem From terminal to modem From terminal to modem From modem to terminal From terminal to modem From terminal to modem From terminal to modem From terminal to modem The control of the DTR output pin is performed by writing the Control Register (US_CR) with the DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable command forces the corresponding pin to its active level, i.e. low. RTS output pin is automatically controlled in this mode The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (US_CSR) are set respectively and can trigger an interrupt. The status is automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter is actually disabled. * 32.6.8 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 492 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.6.8.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 32-38. Normal Mode Configuration RXD Receiver TXD Transmitter 32.6.8.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 32-39. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 32-39. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 32.6.8.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 32-40. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 32-40. Local Loopback Mode Configuration RXD Receiver Transmitter 1 TXD 32.6.8.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 32-41. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. 493 6384D-ATARM-04-May-09 Figure 32-41. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 494 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Register Mapping Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register Reserved FI DI Ratio Register Number of Errors Register Reserved IrDA Filter Register Manchester Encoder Decoder Register Reserved Reserved for PDC Registers Name US_CR US_MR US_IER US_IDR US_IMR US_CSR US_RHR US_THR US_BRGR US_RTOR US_TTGR - US_FIDI US_NER - US_IF US_MAN - - Access Write-only Read-write Write-only Write-only Read-only Read-only Read-only Write-only Read-write Read-write Read-write - Read-write Read-only - Read-write Read-write - - Reset - - - - 0x0 - 0x0 - 0x0 0x0 0x0 - 0x174 - - 0x0 0x30011004 - - Table 32-12. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x2C - 0x3C 0x0040 0x0044 0x0048 0x004C 0x0050 0x5C - 0xFC 0x100 - 0x128 495 6384D-ATARM-04-May-09 32.7.1 Name: USART Control Register US_CR Write-only 30 - 22 - 14 RSTNACK 6 TXEN 29 - 21 - 13 RSTIT 5 RXDIS 28 - 20 - 12 SENDA 4 RXEN 27 - 19 RTSDIS 11 STTTO 3 RSTTX 26 - 18 RTSEN 10 STPBRK 2 RSTRX 25 - 17 DTRDIS 9 STTBRK 1 - 24 - 16 DTREN 8 RSTSTA 0 - Access Type: 31 - 23 - 15 RETTO 7 TXDIS * RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. * RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. * RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. * RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. * TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. * TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. 496 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR. * STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. * STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. * STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR. * SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. * RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. * RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. * RETTO: Rearm Time-out 0: No effect 1: Restart Time-out * DTREN: Data Terminal Ready Enable 0: No effect. 1: Drives the pin DTR at 0. * DTRDIS: Data Terminal Ready Disable 0: No effect. 1: Drives the pin DTR to 1. * RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. 497 6384D-ATARM-04-May-09 * RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1. 498 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.7.2 Name: USART Mode Register US_MR Read-write 30 MODSYNC 22 VAR_SYNC 14 CHMODE 7 CHRL 6 5 USCLKS 29 MAN 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 - 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24 Access Type: 31 ONEBIT 23 - 15 18 CLKO 10 PAR 2 16 MSBF 8 SYNC 0 1 USART_MODE * USART_MODE USART_MODE 0 0 0 0 0 0 1 0 0 0 0 1 1 0 Others 0 0 1 1 0 1 0 0 1 0 1 0 0 0 Mode of the USART Normal RS485 Hardware Handshaking Modem IS07816 Protocol: T = 0 IS07816 Protocol: T = 1 IrDA Reserved * USCLKS: Clock Selection USCLKS 0 0 1 1 0 1 0 1 Selected Clock MCK MCK/DIV (DIV = 8) Reserved SCK * CHRL: Character Length. CHRL 0 0 1 1 0 1 0 1 Character Length 5 bits 6 bits 7 bits 8 bits 499 6384D-ATARM-04-May-09 * SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. * PAR: Parity Type PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode * NBSTOP: Number of Stop Bits NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved * CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input.. Remote Loopback. RXD pin is internally connected to the TXD pin. * MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first. * MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. * CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. * OVER: Oversampling Mode 0: 16x Oversampling. 500 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 1: 8x Oversampling. * INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. * DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. * VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter 0: User defined configuration of command or data sync field depending on SYNC value. 1: The sync field is updated when a character is written into US_THR register. * MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0. * FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. * 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).MAN: Manchester Encoder/Decoder Enable 0: Manchester Encoder/Decoder are disabled. 1: Manchester Encoder/Decoder are enabled. * MODSYNC: Manchester Synchronization Mode 0:The Manchester Start bit is a 0 to 1 transition 1: The Manchester Start bit is a 1 to 0 transition. * ONEBIT: Start Frame Delimiter Selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit. 501 6384D-ATARM-04-May-09 32.7.3 Name: USART Interrupt Enable Register US_IER Write-only 30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 MANE 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 DCDIC 10 ITER 2 RXBRK 25 - 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANE 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 - 23 - 15 - 7 PARE * RXRDY: RXRDY Interrupt Enable * TXRDY: TXRDY Interrupt Enable * RXBRK: Receiver Break Interrupt Enable * ENDRX: End of Receive Transfer Interrupt Enable * ENDTX: End of Transmit Interrupt Enable * OVRE: Overrun Error Interrupt Enable * FRAME: Framing Error Interrupt Enable * PARE: Parity Error Interrupt Enable * TIMEOUT: Time-out Interrupt Enable * TXEMPTY: TXEMPTY Interrupt Enable * ITER: Iteration Interrupt Enable * TXBUFE: Buffer Empty Interrupt Enable * RXBUFF: Buffer Full Interrupt Enable * NACK: Non Acknowledge Interrupt Enable * RIIC: Ring Indicator Input Change Enable * DSRIC: Data Set Ready Input Change Enable * DCDIC: Data Carrier Detect Input Change Interrupt Enable * CTSIC: Clear to Send Input Change Interrupt Enable * MANE: Manchester Error Interrupt Enable 502 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.7.4 Name: USART Interrupt Disable Register US_IDR Write-only 30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 MANE 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 DCDIC 10 ITER 2 RXBRK 25 - 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANE 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 - 23 - 15 - 7 PARE * RXRDY: RXRDY Interrupt Disable * TXRDY: TXRDY Interrupt Disable * RXBRK: Receiver Break Interrupt Disable * ENDRX: End of Receive Transfer Interrupt Disable * ENDTX: End of Transmit Interrupt Disable * OVRE: Overrun Error Interrupt Disable * FRAME: Framing Error Interrupt Disable * PARE: Parity Error Interrupt Disable * TIMEOUT: Time-out Interrupt Disable * TXEMPTY: TXEMPTY Interrupt Disable * ITER: Iteration Interrupt Enable * TXBUFE: Buffer Empty Interrupt Disable * RXBUFF: Buffer Full Interrupt Disable * NACK: Non Acknowledge Interrupt Disable * RIIC: Ring Indicator Input Change Disable * DSRIC: Data Set Ready Input Change Disable * DCDIC: Data Carrier Detect Input Change Interrupt Disable * CTSIC: Clear to Send Input Change Interrupt Disable * MANE: Manchester Error Interrupt Disable 503 6384D-ATARM-04-May-09 32.7.5 Name: USART Interrupt Mask Register US_IMR Read-only 30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 MANE 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 DCDIC 10 ITER 2 RXBRK 25 - 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANE 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 - 23 - 15 - 7 PARE * RXRDY: RXRDY Interrupt Mask * TXRDY: TXRDY Interrupt Mask * RXBRK: Receiver Break Interrupt Mask * ENDRX: End of Receive Transfer Interrupt Mask * ENDTX: End of Transmit Interrupt Mask * OVRE: Overrun Error Interrupt Mask * FRAME: Framing Error Interrupt Mask * PARE: Parity Error Interrupt Mask * TIMEOUT: Time-out Interrupt Mask * TXEMPTY: TXEMPTY Interrupt Mask * ITER: Iteration Interrupt Enable * TXBUFE: Buffer Empty Interrupt Mask * RXBUFF: Buffer Full Interrupt Mask * NACK: Non Acknowledge Interrupt Mask * RIIC: Ring Indicator Input Change Mask * DSRIC: Data Set Ready Input Change Mask * DCDIC: Data Carrier Detect Input Change Interrupt Mask * CTSIC: Clear to Send Input Change Interrupt Mask * MANE: Manchester Error Interrupt Mask 504 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.7.6 Name: USART Channel Status Register US_CSR Read-only 30 - 22 DCD 14 - 6 FRAME 29 - 21 DSR 13 NACK 5 OVRE 28 - 20 RI 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 DCDIC 10 ITER 2 RXBRK 25 - 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANERR 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 - 23 CTS 15 - 7 PARE * RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. * TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. * RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. * ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the Receive PDC channel is inactive. 1: The End of Transfer signal from the Receive PDC channel is active. * ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the Transmit PDC channel is inactive. 1: The End of Transfer signal from the Transmit PDC channel is active. * OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. 505 6384D-ATARM-04-May-09 * FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. * PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. * TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR). * TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. * ITER: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSTSTA. 1: Maximum number of repetitions has been reached since the last RSTSTA. * TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive. 1: The signal Buffer Empty from the Transmit PDC channel is active. * RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDC channel is inactive. 1: The signal Buffer Full from the Receive PDC channel is active. * NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. * RIIC: Ring Indicator Input Change Flag 0: No input change has been detected on the RI pin since the last read of US_CSR. 1: At least one input change has been detected on the RI pin since the last read of US_CSR. * DSRIC: Data Set Ready Input Change Flag 0: No input change has been detected on the DSR pin since the last read of US_CSR. 1: At least one input change has been detected on the DSR pin since the last read of US_CSR. * DCDIC: Data Carrier Detect Input Change Flag 0: No input change has been detected on the DCD pin since the last read of US_CSR. 1: At least one input change has been detected on the DCD pin since the last read of US_CSR. * CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 506 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. * RI: Image of RI Input 0: RI is at 0. 1: RI is at 1. * DSR: Image of DSR Input 0: DSR is at 0 1: DSR is at 1. * DCD: Image of DCD Input 0: DCD is at 0. 1: DCD is at 1. * CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1. * MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA. 507 6384D-ATARM-04-May-09 32.7.7 Name: USART Receive Holding Register US_RHR Read-only 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RXCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 RXCHR 0 Access Type: 31 - 23 - 15 RXSYNH 7 * RXCHR: Received Character Last character received if RXRDY is set. * RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. 508 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.7.8 Name: USART Transmit Holding Register US_THR Write-only 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TXCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 TXCHR 0 Access Type: 31 - 23 - 15 TXSYNH 7 * TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. * TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC. 509 6384D-ATARM-04-May-09 32.7.9 Name: USART Baud Rate Generator Register US_BRGR Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CD 7 6 5 4 CD 3 2 1 0 27 - 19 - 11 26 - 18 25 - 17 FP- 9 24 - 16 Access Type: 31 - 23 - 15 10 8 * CD: Clock Divider USART_MODE ISO7816 SYNC = 0 CD 0 1 to 65535 Baud Rate = Selected Clock/16/CD OVER = 0 OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO SYNC = 1 USART_MODE = ISO7816 * FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8. 510 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.7.10 Name: USART Receiver Time-out Register US_RTOR Read-write 30 29 28 27 26 25 24 Access Type: 31 - 23 - 15 - 22 - 14 - 21 - 13 - 20 - 12 TO - 19 - 11 - 18 - 10 - 17 - 9 - 16 - 8 7 6 5 4 TO 3 2 1 0 * TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. 511 6384D-ATARM-04-May-09 32.7.11 Name: USART Transmitter Timeguard Register US_TTGR Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TG 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 Access Type: 31 - 23 - 15 - 7 * TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. 512 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.7.12 Name: USART FI DI RATIO Register US_FIDI Read-write 0x174 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FI_DI_RATIO 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 FI_DI_RATIO 1 24 - 16 - 8 Access Type: Reset Value: 31 - 23 - 15 - 7 2 0 * FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO. 32.7.13 Name: USART Number of Errors Register US_NER Read-only 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 NB_ERRORS 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 Access Type: 31 - 23 - 15 - 7 * NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. 513 6384D-ATARM-04-May-09 32.7.14 Name: USART IrDA FILTER Register US_IF Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 IRDA_FILTER 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 Access Type: 31 - 23 - 15 - 7 * IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator. 514 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 32.7.15 Name: USART Manchester Configuration Register US_MAN Read-write 30 DRIFT 22 - 14 - 6 - 29 1 21 - 13 - 5 - 28 RX_MPOL 20 - 12 TX_MPOL 4 - 27 - 19 26 - 18 RX_PL 11 - 3 10 - 2 TX_PL 9 TX_PP 1 0 8 25 RX_PP 17 16 24 Access Type: 31 - 23 - 15 - 7 - * TX_PL: Transmitter Preamble Length 0: The Transmitter Preamble pattern generation is disabled 1 - 15: The Preamble Length is TX_PL x Bit Period * TX_PP: Transmitter Preamble Pattern TX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (TX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO * TX_MPOL: Transmitter Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. * RX_PL: Receiver Preamble Length 0: The receiver preamble pattern detection is disabled 1 - 15: The detected preamble length is RX_PL x Bit Period * RX_PP: Receiver Preamble Pattern detected RX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (RX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO 515 6384D-ATARM-04-May-09 * RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. * DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled. 516 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 33. Synchronous Serial Controller (SSC) 33.1 Overview The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC's high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following: * CODEC's in master or slave mode * DAC through dedicated serial interface, particularly I2S * Magnetic card reader 517 6384D-ATARM-04-May-09 33.2 Block Diagram Figure 33-1. Block Diagram System Bus APB Bridge PDC Peripheral Bus TF TK TD SSC Interface PIO RF RK Interrupt Control RD PMC MCK SSC Interrupt 33.3 Application Block Diagram Figure 33-2. Application Block Diagram OS or RTOS Driver Power Management SSC Time Slot Management Frame Management Interrupt Management Test Management Serial AUDIO Codec Line Interface 518 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 33.4 Pin Name List I/O Lines Description Pin Description Receiver Frame Synchro Receiver Clock Receiver Data Transmitter Frame Synchro Transmitter Clock Transmitter Data Type Input/Output Input/Output Input Input/Output Input/Output Output Table 33-1. Pin Name RF RK RD TF TK TD 33.5 33.5.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode. 33.5.2 Power Management The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. Interrupt The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register. 33.5.3 33.6 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2. 519 6384D-ATARM-04-May-09 Figure 33-3. SSC Functional Block Diagram Transmitter Clock Output Controller TK MCK Clock Divider TK Input RX clock TF RF Start Selector TX PDC Transmit Clock Controller TX clock Frame Sync Controller TF Transmit Shift Register Transmit Holding Register Transmit Sync Holding Register TD APB User Interface Load Shift Receiver Clock Output Controller RK RK Input TX Clock RF TF Start Selector Receive Clock RX Clock Controller Frame Sync Controller RF Receive Shift Register Receive Holding Register Receive Sync Holding Register RD RX PDC PDC Interrupt Control Load Shift AIC 33.6.1 Clock Management The transmitter clock can be generated by: * an external clock received on the TK I/O pad * the receiver clock * the internal clock divider The receiver clock can be generated by: * an external clock received on the RK I/O pad * the transmitter clock * the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. 520 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 33.6.1.1 Clock Divider Figure 33-4. Divided Clock Block Diagram Clock Divider SSC_CMR MCK /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd. Figure 33-5. Divided Clock Generation Master Clock Divided Clock DIV = 1 Divided Clock Frequency = MCK/2 Master Clock Divided Clock DIV = 3 Divided Clock Frequency = MCK/6 Table 33-2. Maximum MCK / 2 Minimum MCK / 8190 33.6.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. 521 6384D-ATARM-04-May-09 The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Figure 33-6. Transmitter Clock Management TK (pin) MUX Receiver Clock Tri_state Controller Clock Output Divider Clock CKO Data Transfer CKS INV MUX Tri-state Controller Transmitter Clock CKI CKG 33.6.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results. 522 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 33-7. Receiver Clock Management RK (pin) Tri-state Controller MUX Transmitter Clock Clock Output Divider Clock CKO Data Transfer CKS INV MUX Tri-state Controller Receiver Clock CKI CKG 33.6.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is: - Master Clock divided by 2 if Receiver Frame Synchro is input - Master Clock divided by 3 if Receiver Frame Synchro is output In addition, the maximum clock speed allowed on the TK pin is: - Master Clock divided by 6 if Transmit Frame Synchro is input - Master Clock divided by 2 if Transmit Frame Synchro is output 33.6.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See "Start" on page 525. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See "Frame Sync" on page 527. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. 523 6384D-ATARM-04-May-09 Figure 33-8. Transmitter Block Diagram SSC_CR.TXEN SSC_SR.TXEN SSC_CR.TXDIS SSC_TFMR.DATDEF 1 RF Transmitter Clock TF SSC_TFMR.MSBF 0 SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB TD Start Selector Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY SSC_TFMR.DATLEN SSC_THR 0 1 SSC_TSHR SSC_TFMR.FSLEN 33.6.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See "Start" on page 525. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See "Frame Sync" on page 527. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register. 524 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 33-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS RF Receiver Clock TF SSC_RFMR.MSBF SSC_RFMR.DATNB Start Selector Receive Shift Register RD SSC_RSHR SSC_RCMR.STTDLY SSC_RFMR.FSLEN SSC_RHR SSC_RFMR.DATLEN 33.6.4 Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable: * Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled. * Synchronously with the transmitter/receiver * On detection of a falling/rising edge on TF/RF * On detection of a low level/high level on TF/RF * On detection of a level change or an edge on TF/RF A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions. Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). 525 6384D-ATARM-04-May-09 Figure 33-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF TD (Output) TD (Output) X BO B1 STTDLY Start = Falling Edge on TF X BO B1 STTDLY X BO B1 STTDLY Start = High Level on TF TD (Output) TD (Output) TD (Output) TD (Output) X Start = Rising Edge on TF BO B1 STTDLY Start = Level Change on TF X BO B1 BO B1 STTDLY Start = Any Edge on TF X BO B1 BO B1 STTDLY Figure 33-11. Receive Pulse/Edge Start Modes RK RF (Input) Start = Low Level on RF RD (Input) RD (Input) X BO B1 STTDLY Start = Falling Edge on RF X BO B1 STTDLY X BO B1 STTDLY Start = High Level on RF RD (Input) RD (Input) RD (Input) RD (Input) X Start = Rising Edge on RF BO B1 STTDLY Start = Level Change on RF X BO B1 BO B1 STTDLY Start = Any Edge on RF X BO B1 BO B1 STTDLY 526 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 33.6.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. * Programmable low or high levels during data transfer are supported. * Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 256 bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR. 33.6.5.1 Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out. 33.6.5.2 Frame Sync Edge Detection The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). Receive Compare Modes Figure 33-12. Receive Compare Modes RK 33.6.6 RD (Input) CMP0 CMP1 CMP2 CMP3 Start Ignored B0 B1 B2 FSLEN Up to 16 Bits (4 in This Example) STDLY DATLEN 527 6384D-ATARM-04-May-09 33.6.6.1 Compare Functions Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: * the event that starts the data transfer (START) * the delay in number of bit periods between the start event and the first data bit (STTDLY) * the length of the data (DATLEN) * the number of data to be transferred for each start event (DATNB). * the length of synchronization transferred for each start event (FSLEN) * the bit sense: most or lowest significant bit first (MSBF) Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR. 33.6.7 528 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 33-3. Transmitter SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TCMR SSC_TCMR SSC_RCMR SSC_RCMR Data Frame Registers Receiver SSC_RFMR SSC_RFMR SSC_RFMR SSC_RFMR Field DATLEN DATNB MSBF FSLEN DATDEF FSDEN PERIOD STTDLY Up to 512 Up to 255 Up to 16 0 or 1 Length Up to 32 Up to 16 Comment Size of word Number of words transmitted in frame Most significant bit first Size of Synchro data register Data default value ended Enable send SSC_TSHR Frame size Size of transmit start delay Figure 33-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start PERIOD TF/RF (1) Start FSLEN TD (If FSDEN = 1) Sync Data Default Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Default FromDATDEF Default From DATDEF Ignored Sync Data Sync Data From SSC_TSHR FromDATDEF Default From DATDEF Sync Data To SSC_RSHR STTDLY Ignored TD (If FSDEN = 0) RD DATNB Note: 1. Example of input on falling edge of TF/RF. Figure 33-14. Transmit Frame Format in Continuous Mode Start TD Data From SSC_THR DATLEN Data From SSC_THR DATLEN Default Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR 529 6384D-ATARM-04-May-09 Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 33-15. Receive Frame Format in Continuous Mode Start = Enable Receiver RD Data To SSC_RHR DATLEN Data To SSC_RHR DATLEN Note: 1. STTDLY is set to 0. 33.6.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 33.6.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC. Figure 33-16. Interrupt Block Diagram SSC_IMR SSC_IER PDC TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC RXBUFF ENDRX Receiver RXRDY OVRUN RXSYNC Interrupt Control Set SSC_IDR Clear SSC Interrupt 530 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 33.7 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 33-17. Audio Application Block Diagram Clock SCK TK Word Select WS TF Data SD SSC TD RD RF RK I2S RECEIVER Clock SCK Word Select WS Data SD MSB Left Channel LSB MSB Right Channel Figure 33-18. Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF Serial Data Out SSC TD Serial Data In RD RF RK CODEC Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Serial Data Out Dend Serial Data In 531 6384D-ATARM-04-May-09 Figure 33-19. Time Slot Application Block Diagram SCLK TK FSYNC TF Data Out TD SSC RD RF RK Data in CODEC First Time Slot CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out First Time Slot Dstart Second Time Slot Dend Serial Data in 532 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 33.8 Syncrhronous Serial Controller (SSC) User Interface Register Mapping Register Control Register Clock Mode Register Reserved Reserved Receive Clock Mode Register Receive Frame Mode Register Transmit Clock Mode Register Transmit Frame Mode Register Receive Holding Register Transmit Holding Register Reserved Reserved Receive Sync. Holding Register Transmit Sync. Holding Register Receive Compare 0 Register Receive Compare 1 Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for Peripheral Data Controller (PDC) Name SSC_CR SSC_CMR - - SSC_RCMR SSC_RFMR SSC_TCMR SSC_TFMR SSC_RHR SSC_THR - - SSC_RSHR SSC_TSHR SSC_RC0R SSC_RC1R SSC_SR SSC_IER SSC_IDR SSC_IMR - - Access Write Read-write - - Read-write Read-write Read-write Read-write Read Write - - Read Read-write Read-write Read-write Read Write Write Read - - Reset - 0x0 - - 0x0 0x0 0x0 0x0 0x0 - - - 0x0 0x0 0x0 0x0 0x000000CC - - 0x0 - - Table 33-4. Offset 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50-0xFC 0x100- 0x124 533 6384D-ATARM-04-May-09 33.8.1 Name: SSC Control Register SSC_CR Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 TXDIS 1 RXDIS 24 - 16 - 8 TXEN 0 RXEN Access Type: 31 - 23 - 15 SWRST 7 - * RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set. * RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive. If a character is currently being received, disables at end of current character reception. * TXEN: Transmit Enable 0 = No effect. 1 = Enables Transmit if TXDIS is not set. * TXDIS: Transmit Disable 0 = No effect. 1 = Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission. * SWRST: Software Reset 0 = No effect. 1 = Performs a software reset. Has priority on any other bit in SSC_CR. 534 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 33.8.2 Name: SSC Clock Mode Register SSC_CMR Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 DIV 27 - 19 - 11 26 - 18 - 10 DIV 3 2 1 0 25 - 17 - 9 24 - 16 - 8 Access Type: 31 - 23 - 15 - 7 * DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190. 535 6384D-ATARM-04-May-09 33.8.3 Name: SSC Receive Clock Mode Register SSC_RCMR Read-write 30 29 28 PERIOD 27 26 25 24 Access Type: 31 23 22 21 20 STTDLY 19 18 17 16 15 - 7 CKG 14 - 6 13 - 5 CKI 12 STOP 4 11 10 START 9 8 3 CKO 2 1 CKS 0 * CKS: Receive Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Receive Clock Divided Clock TK Clock signal RK pin Reserved * CKO: Receive Clock Output Mode Selection CKO 0x0 0x1 0x2 0x3-0x7 Receive Clock Output Mode None Continuous Receive Clock Receive Clock only during data transfers Reserved RK pin Input-only Output Output * CKI: Receive Clock Inversion 0 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge. CKI affects only the Receive Clock and not the output clock signal. 536 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * CKG: Receive Clock Gating Selection CKG 0x0 0x1 0x2 0x3 Receive Clock Gating None, continuous clock Receive Clock enabled only if RF Low Receive Clock enabled only if RF High Reserved * START: Receive Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9-0xF Receive Start Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Transmit start Detection of a low level on RF signal Detection of a high level on RF signal Detection of a falling edge on RF signal Detection of a rising edge on RF signal Detection of any level change on RF signal Detection of any edge on RF signal Compare 0 Reserved * STOP: Receive Stop Selection 0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected. * STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. * PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock. 537 6384D-ATARM-04-May-09 33.8.4 Name: SSC Receive Frame Mode Register SSC_RFMR Read-write 30 FSLEN_EXT 22 29 FSLEN_EXT 21 FSOS 13 - 5 LOOP 28 FSLEN_EXT Access Type: 31 FSLEN_EXT 23 - 15 - 7 MSBF 27 - 19 26 - 18 FSLEN 25 - 17 24 FSEDGE 16 20 14 - 6 - 12 - 4 11 10 DATNB 9 8 3 2 DATLEN 1 0 * DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. * LOOP: Loop Mode 0 = Normal operating mode. 1 = RD is driven by TD, RF is driven by TF and TK drives RK. * MSBF: Most Significant Bit First 0 = The lowest significant bit of the data register is sampled first in the bit stream. 1 = The most significant bit of the data register is sampled first in the bit stream. * DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). * FSLEN: Receive Frame Sync Length This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal. Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Receive Clock periods. 538 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * FSOS: Receive Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Receive Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved RF Pin Input-only Output Output Output Output Output Undefined * FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register. FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection * FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description on page 538. 539 6384D-ATARM-04-May-09 33.8.5 Name: SSC Transmit Clock Mode Register SSC_TCMR Read-write 30 29 28 PERIOD 27 26 25 24 Access Type: 31 23 22 21 20 STTDLY 19 18 17 16 15 - 7 CKG 14 - 6 13 - 5 CKI 12 - 4 11 10 START 9 8 3 CKO 2 1 CKS 0 * CKS: Transmit Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Transmit Clock Divided Clock RK Clock signal TK Pin Reserved * CKO: Transmit Clock Output Mode Selection CKO 0x0 0x1 0x2 0x3-0x7 Transmit Clock Output Mode None Continuous Transmit Clock Transmit Clock only during data transfers Reserved TK pin Input-only Output Output * CKI: Transmit Clock Inversion 0 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. CKI affects only the Transmit Clock and not the output clock signal. 540 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * CKG: Transmit Clock Gating Selection CKG 0x0 0x1 0x2 0x3 Transmit Clock Gating None, continuous clock Transmit Clock enabled only if TF Low Transmit Clock enabled only if TF High Reserved * START: Transmit Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 - 0xF Transmit Start Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. Receive start Detection of a low level on TF signal Detection of a high level on TF signal Detection of a falling edge on TF signal Detection of a rising edge on TF signal Detection of any level change on TF signal Detection of any edge on TF signal Reserved * STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. * PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock. 541 6384D-ATARM-04-May-09 33.8.6 Name: SSC Transmit Frame Mode Register SSC_TFMR Read-write 30 FSLEN_EXT 22 29 FSLEN_EXT 21 FSOS 13 - 5 DATDEF 28 FSLEN_EXT Access Type: 31 FSLEN_EXT 23 FSDEN 15 - 7 MSBF 27 - 19 26 - 18 FSLEN 25 - 17 24 FSEDGE 16 20 14 - 6 - 12 - 4 11 10 DATNB 9 8 3 2 DATLEN 1 0 * DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. * DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. * MSBF: Most Significant Bit First 0 = The lowest significant bit of the data register is shifted out first in the bit stream. 1 = The most significant bit of the data register is shifted out first in the bit stream. * DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1). * FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal. Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Transmit Clock periods. 542 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * FSOS: Transmit Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Transmit Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved TF Pin Input-only Output Output Output Output Output Undefined * FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal. 1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. * FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register). FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection * FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description on page 542. 543 6384D-ATARM-04-May-09 33.8.7 Name: SSC Receive Holding Register SSC_RHR Read-only 30 29 28 RDAT 27 26 25 24 Access Type: 31 23 22 21 20 RDAT 19 18 17 16 15 14 13 12 RDAT 11 10 9 8 7 6 5 4 RDAT 3 2 1 0 * RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 33.8.8 Name: SSC Transmit Holding Register SSC_THR Write-only 30 29 28 TDAT 27 26 25 24 Access Type: 31 23 22 21 20 TDAT 19 18 17 16 15 14 13 12 TDAT 11 10 9 8 7 6 5 4 TDAT 3 2 1 0 * TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. 544 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 33.8.9 Name: SSC Receive Synchronization Holding Register SSC_RSHR Read-only 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RSDAT 7 6 5 4 RSDAT 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 Access Type: 31 - 23 - 15 * RSDAT: Receive Synchronization Data 33.8.10 Name: SSC Transmit Synchronization Holding Register SSC_TSHR Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 TSDAT 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 Access Type: 31 - 23 - 15 7 6 5 4 TSDAT 3 2 1 0 * TSDAT: Transmit Synchronization Data 545 6384D-ATARM-04-May-09 33.8.11 Name: SSC Receive Compare 0 Register SSC_RC0R Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CP0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 Access Type: 31 - 23 - 15 7 6 5 4 CP0 3 2 1 0 * CP0: Receive Compare Data 0 33.8.12 Name: SSC Receive Compare 1 Register SSC_RC1R Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CP1 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 Access Type: 31 - 23 - 15 7 6 5 4 CP1 3 2 1 0 * CP1: Receive Compare Data 1 546 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 33.8.13 Name: SSC Status Register SSC_SR Read-only 30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 RXEN 9 CP1 1 TXEMPTY 24 - 16 TXEN 8 CP0 0 TXRDY Access Type: 31 - 23 - 15 - 7 RXBUFF * TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty. * TXEMPTY: Transmit Empty 0 = Data remains in SSC_THR or is currently transmitted from TSR. 1 = Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted. * ENDTX: End of Transmission 0 = The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1 = The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR. * TXBUFE: Transmit Buffer Empty 0 = SSC_TCR or SSC_TNCR have a value other than 0. 1 = Both SSC_TCR and SSC_TNCR have a value of 0. * RXRDY: Receive Ready 0 = SSC_RHR is empty. 1 = Data has been received and loaded in SSC_RHR. * OVRUN: Receive Overrun 0 = No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1 = Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. * ENDRX: End of Reception 0 = Data is written on the Receive Counter Register or Receive Next Counter Register. 1 = End of PDC transfer when Receive Counter Register has arrived at zero. 547 6384D-ATARM-04-May-09 * RXBUFF: Receive Buffer Full 0 = SSC_RCR or SSC_RNCR have a value other than 0. 1 = Both SSC_RCR and SSC_RNCR have a value of 0. * CP0: Compare 0 0 = A compare 0 has not occurred since the last read of the Status Register. 1 = A compare 0 has occurred since the last read of the Status Register. * CP1: Compare 1 0 = A compare 1 has not occurred since the last read of the Status Register. 1 = A compare 1 has occurred since the last read of the Status Register. * TXSYN: Transmit Sync 0 = A Tx Sync has not occurred since the last read of the Status Register. 1 = A Tx Sync has occurred since the last read of the Status Register. * RXSYN: Receive Sync 0 = An Rx Sync has not occurred since the last read of the Status Register. 1 = An Rx Sync has occurred since the last read of the Status Register. * TXEN: Transmit Enable 0 = Transmit is disabled. 1 = Transmit is enabled. * RXEN: Receive Enable 0 = Receive is disabled. 1 = Receive is enabled. 548 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 33.8.14 Name: SSC Interrupt Enable Register SSC_IER Write-only 30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 - 9 CP1 1 TXEMPTY 24 - 16 - 8 CP0 0 TXRDY Access Type: 31 - 23 - 15 - 7 RXBUFF * TXRDY: Transmit Ready Interrupt Enable 0 = No effect. 1 = Enables the Transmit Ready Interrupt. * TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Empty Interrupt. * ENDTX: End of Transmission Interrupt Enable 0 = No effect. 1 = Enables the End of Transmission Interrupt. * TXBUFE: Transmit Buffer Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Buffer Empty Interrupt * RXRDY: Receive Ready Interrupt Enable 0 = No effect. 1 = Enables the Receive Ready Interrupt. * OVRUN: Receive Overrun Interrupt Enable 0 = No effect. 1 = Enables the Receive Overrun Interrupt. * ENDRX: End of Reception Interrupt Enable 0 = No effect. 1 = Enables the End of Reception Interrupt. 549 6384D-ATARM-04-May-09 * RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the Receive Buffer Full Interrupt. * CP0: Compare 0 Interrupt Enable 0 = No effect. 1 = Enables the Compare 0 Interrupt. * CP1: Compare 1 Interrupt Enable 0 = No effect. 1 = Enables the Compare 1 Interrupt. * TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Enables the Tx Sync Interrupt. * RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Enables the Rx Sync Interrupt. 550 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 33.8.15 Name: SSC Interrupt Disable Register SSC_IDR Write-only 30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 - 9 CP1 1 TXEMPTY 24 - 16 - 8 CP0 0 TXRDY Access Type: 31 - 23 - 15 - 7 RXBUFF * TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt. * TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Empty Interrupt. * ENDTX: End of Transmission Interrupt Disable 0 = No effect. 1 = Disables the End of Transmission Interrupt. * TXBUFE: Transmit Buffer Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Buffer Empty Interrupt. * RXRDY: Receive Ready Interrupt Disable 0 = No effect. 1 = Disables the Receive Ready Interrupt. * OVRUN: Receive Overrun Interrupt Disable 0 = No effect. 1 = Disables the Receive Overrun Interrupt. * ENDRX: End of Reception Interrupt Disable 0 = No effect. 1 = Disables the End of Reception Interrupt. 551 6384D-ATARM-04-May-09 * RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the Receive Buffer Full Interrupt. * CP0: Compare 0 Interrupt Disable 0 = No effect. 1 = Disables the Compare 0 Interrupt. * CP1: Compare 1 Interrupt Disable 0 = No effect. 1 = Disables the Compare 1 Interrupt. * TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Disables the Tx Sync Interrupt. * RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Disables the Rx Sync Interrupt. 552 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 33.8.16 Name: SSC Interrupt Mask Register SSC_IMR Read-only 30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 - 9 CP1 1 TXEMPTY 24 - 16 - 8 CP0 0 TXRDY Access Type: 31 - 23 - 15 - 7 RXBUF * TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled. * TXEMPTY: Transmit Empty Interrupt Mask 0 = The Transmit Empty Interrupt is disabled. 1 = The Transmit Empty Interrupt is enabled. * ENDTX: End of Transmission Interrupt Mask 0 = The End of Transmission Interrupt is disabled. 1 = The End of Transmission Interrupt is enabled. * TXBUFE: Transmit Buffer Empty Interrupt Mask 0 = The Transmit Buffer Empty Interrupt is disabled. 1 = The Transmit Buffer Empty Interrupt is enabled. * RXRDY: Receive Ready Interrupt Mask 0 = The Receive Ready Interrupt is disabled. 1 = The Receive Ready Interrupt is enabled. * OVRUN: Receive Overrun Interrupt Mask 0 = The Receive Overrun Interrupt is disabled. 1 = The Receive Overrun Interrupt is enabled. * ENDRX: End of Reception Interrupt Mask 0 = The End of Reception Interrupt is disabled. 1 = The End of Reception Interrupt is enabled. 553 6384D-ATARM-04-May-09 * RXBUFF: Receive Buffer Full Interrupt Mask 0 = The Receive Buffer Full Interrupt is disabled. 1 = The Receive Buffer Full Interrupt is enabled. * CP0: Compare 0 Interrupt Mask 0 = The Compare 0 Interrupt is disabled. 1 = The Compare 0 Interrupt is enabled. * CP1: Compare 1 Interrupt Mask 0 = The Compare 1 Interrupt is disabled. 1 = The Compare 1 Interrupt is enabled. * TXSYN: Tx Sync Interrupt Mask 0 = The Tx Sync Interrupt is disabled. 1 = The Tx Sync Interrupt is enabled. * RXSYN: Rx Sync Interrupt Mask 0 = The Rx Sync Interrupt is disabled. 1 = The Rx Sync Interrupt is enabled. 554 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 34. Timer Counter (TC) 34.1 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Table 34-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2 Table 34-1. Name Timer Counter Clock Assignment Definition MCK/2 MCK/8 MCK/32 MCK/128 SLCK TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 555 6384D-ATARM-04-May-09 34.2 Block Diagram Figure 34-1. Timer Counter Block Diagram Parallel I/O Controller TCLK0 TIMER_CLOCK2 TIMER_CLOCK1 TIOA1 TIMER_CLOCK3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA2 TCLK1 XC0 XC1 XC2 TC0XC0S Timer/Counter Channel 0 TIOA TIOA0 TIOB TIMER_CLOCK4 TIMER_CLOCK5 TCLK2 TIOB0 SYNC INT0 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S SYNC Timer/Counter Channel 1 TIOA TIOA1 TIOB TIOB1 INT1 TIOA1 TIOB1 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 XC0 XC1 XC2 TC2XC2S Timer/Counter Channel 2 TIOA TIOA2 TIOB TIOB2 SYNC TIOA2 TIOB2 INT2 Timer Counter Advanced Interrupt Controller Table 34-2. Signal Name Description Signal Name XC0, XC1, XC2 TIOA Description External Clock Inputs Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output Interrupt Signal Output Synchronization Input Signal Block/Channel Channel Signal TIOB INT SYNC 556 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 34.3 Pin Name List Table 34-3. Pin Name TCLK0-TCLK2 TIOA0-TIOA2 TIOB0-TIOB2 TC pin list Description External Clock Input I/O Line A I/O Line B Type Input I/O I/O 34.4 34.4.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 34.4.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. Interrupt The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the AIC before configuring the TC. 34.4.3 557 6384D-ATARM-04-May-09 34.5 34.5.1 Functional Description TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 34-4 on page 571. 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 34.5.2 34.5.3 Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 34-2 on page 559. Each channel can independently select an internal or external clock source for its counter: * * Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5 External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). See Figure 34-3 on page 559 Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock 558 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 34-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TIOA1 TIOA2 XC0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 TIOA0 TCLK0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 TIOA0 TIOA2 XC0 = TCLK2 XC1 XC2 = TCLK2 TIOB1 TIOA1 SYNC TC2XC2S Timer/Counter Channel 2 XC0 = TCLK0 TIOA2 TCLK2 TIOA0 TIOA1 XC1 = TCLK1 XC2 TIOB2 SYNC Figure 34-3. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI Selected Clock BURST 1 559 6384D-ATARM-04-May-09 34.5.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 34-4. * The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. * Figure 34-4. Clock Control Selected Clock Trigger CLKSTA CLKEN CLKDIS Q Q S R S R Counter Clock Stop Event Disable Event 34.5.5 TC Operating Modes Each channel can independently operate in two different modes: * * Capture Mode provides measurement on signals. Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 34.5.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: 560 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * * Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. * The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 34.5.7 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 34-5 shows the configuration of the TC channel when programmed in Capture Mode. 34.5.8 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. 34.5.9 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. 561 6384D-ATARM-04-May-09 Figure 34-5. Capture Mode 562 TCCLKS CLKI CLKSTA CLKEN CLKDIS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 Q Q R S R S TIMER_CLOCK5 XC0 XC1 LDBSTOP BURST LDBDIS XC2 Register C 1 16-bit Counter CLK OVF RESET Trig ABETRG ETRGEDG Edge Detector LDRA LDRB CPCTRG Capture Register A SWTRG AT91SAM9G20 Preliminary Capture Register B Compare RC = CPCS LOVRS LDRAS LDRBS ETRGS COVFS TC1_SR SYNC MTIOB TIOB MTIOA If RA is not loaded or RB is Loaded Edge Detector If RA is Loaded Edge Detector TC1_IMR TIOA Timer/Counter Channel 6384D-ATARM-04-May-09 INT AT91SAM9G20 Preliminary 34.5.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 34-6 shows the configuration of the TC channel when programmed in Waveform Operating Mode. 34.5.11 Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 563 6384D-ATARM-04-May-09 BURST Register A WAVSEL Register B Edge Detector TIOB TC1_IMR BSWTRG Timer/Counter Channel 6384D-ATARM-04-May-09 INT Output Controller AT91SAM9G20 Preliminary TCCLKS CLKSTA CLKI CLKEN CLKDIS ACPC Register C ASWTRG 1 16-bit Counter CLK RESET OVF Compare RA = Compare RB = Compare RC = SWTRG BCPC Trig BCPB WAVSEL EEVT BEEVT EEVTEDG ENETRG CPCS CPAS CPBS ETRGS COVFS TC1_SR MTIOB SYNC Output Controller 564 Q CPCDIS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 S R ACPA MTIOA TIMER_CLOCK5 Q R CPCSTOP S XC0 XC1 Figure 34-6. Waveform Mode XC2 AEEVT TIOA TIOB AT91SAM9G20 Preliminary 34.5.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 34-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 34-8. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 34-7. WAVSEL= 00 without trigger Counter Value 0xFFFF Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 565 6384D-ATARM-04-May-09 Figure 34-8. WAVSEL= 00 with trigger Counter Value 0xFFFF Counter cleared by trigger Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 34.5.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 34-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 34-10. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 34-9. WAVSEL = 10 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA 566 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 34-10. WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger RA Waveform Examples TIOB Time TIOA 34.5.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 34-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 34-12. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). 567 6384D-ATARM-04-May-09 Figure 34-11. WAVSEL = 01 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA Figure 34-12. WAVSEL = 01 With Trigger Counter Value 0xFFFF Counter decremented by trigger RC RB Counter decremented by compare match with 0xFFFF Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 34.5.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 34-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 34-14. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). 568 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 34-13. WAVSEL = 11 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA Figure 34-14. WAVSEL = 11 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 569 6384D-ATARM-04-May-09 34.5.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. 34.5.13 Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 570 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 34.6 Timer Counter (TC) User Interface Register Mapping Offset(1) 0x00 + channel * 0x40 + 0x00 0x00 + channel * 0x40 + 0x04 0x00 + channel * 0x40 + 0x08 0x00 + channel * 0x40 + 0x0C 0x00 + channel * 0x40 + 0x10 0x00 + channel * 0x40 + 0x14 0x00 + channel * 0x40 + 0x18 0x00 + channel * 0x40 + 0x1C 0x00 + channel * 0x40 + 0x20 0x00 + channel * 0x40 + 0x24 0x00 + channel * 0x40 + 0x28 0x00 + channel * 0x40 + 0x2C 0xC0 0xC4 0xFC Notes: 2. Read-only if WAVE = 0 Register Channel Control Register Channel Mode Register Reserved Reserved Counter Value Register A Register B Register C Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Block Control Register Block Mode Register Reserved TC_CV TC_RA TC_RB TC_RC TC_SR TC_IER TC_IDR TC_IMR TC_BCR TC_BMR - Read-only Read-write Read-write (2) (2) Table 34-4. Name TC_CCR TC_CMR Access Write-only Read-write Reset - 0 0 0 0 0 0 - - 0 - 0 - Read-write Read-only Write-only Write-only Read-only Write-only Read-write - 1. Channel index ranges from 0 to 2. 571 6384D-ATARM-04-May-09 34.6.1 TC Block Control Register Register Name:TC_BCR Access Type:Write-only 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 SYNC * SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 572 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 34.6.2 TC Block Mode Register Register Name:TC_BMR Access Type:Read-write 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 TC2XC2S 28 - 20 - 12 - 4 27 - 19 - 11 - 3 TC1XC1S 26 - 18 - 10 - 2 25 - 17 - 9 - 1 TC0XC0S 24 - 16 - 8 - 0 * TC0XC0S: External Clock Signal 0 Selection TC0XC0S 0 0 1 1 0 1 0 1 Signal Connected to XC0 TCLK0 none TIOA1 TIOA2 * TC1XC1S: External Clock Signal 1 Selection TC1XC1S 0 0 1 1 0 1 0 1 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2 * TC2XC2S: External Clock Signal 2 Selection TC2XC2S 0 0 1 1 0 1 0 1 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1 573 6384D-ATARM-04-May-09 34.6.3 TC Channel Control Register Register Name:TC_CCRx [x=0..2] Access Type:Write-only 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 SWTRG 25 - 17 - 9 - 1 CLKDIS 24 - 16 - 8 - 0 CLKEN * CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. * CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. * SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and the clock is started. 574 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 34.6.4 TC Channel Mode Register: Capture Mode Register Name:TC_CMRx [x=0..2] (WAVE = 0) Access Type:Read-write 31 - 23 - 15 WAVE 7 LDBDIS 30 - 22 - 14 CPCTRG 6 LDBSTOP 29 - 21 - 13 - 5 BURST 28 - 20 - 12 - 4 11 - 3 CLKI 27 - 19 LDRB 10 ABETRG 2 1 TCCLKS 9 ETRGEDG 0 26 - 18 25 - 17 LDRA 8 24 - 16 * TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 * CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. * BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. * LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. 575 6384D-ATARM-04-May-09 * LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. * ETRGEDG: External Trigger Edge Selection ETRGEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge * ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. * CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. * WAVE 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). * LDRA: RA Loading Selection LDRA 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA * LDRB: RB Loading Selection LDRB 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA 576 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 34.6.5 TC Channel Mode Register: Waveform Mode Register Name:TC_CMRx [x=0..2] (WAVE = 1) Access Type:Read-write 31 BSWTRG 23 ASWTRG 15 WAVE 7 CPCDIS 6 CPCSTOP 14 WAVSEL 5 BURST 13 22 21 AEEVT 12 ENETRG 4 3 CLKI 11 EEVT 2 1 TCCLKS 30 29 BEEVT 20 19 ACPC 10 9 EEVTEDG 0 28 27 BCPC 18 17 ACPA 8 26 25 BCPB 16 24 * TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 * CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. * BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. * CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. 577 6384D-ATARM-04-May-09 * CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. * EEVTEDG: External Event Edge Selection EEVTEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge * EEVT: External Event Selection EEVT 0 0 1 1 Note: 0 1 0 1 Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input (1) output output output 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. * ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock. * WAVSEL: Waveform Selection WAVSEL 0 1 0 1 0 0 1 1 Effect UP mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare * WAVE 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. 578 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * ACPA: RA Compare Effect on TIOA ACPA 0 0 1 1 0 1 0 1 Effect none set clear toggle * ACPC: RC Compare Effect on TIOA ACPC 0 0 1 1 0 1 0 1 Effect none set clear toggle * AEEVT: External Event Effect on TIOA AEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle * ASWTRG: Software Trigger Effect on TIOA ASWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle * BCPB: RB Compare Effect on TIOB BCPB 0 0 1 1 0 1 0 1 Effect none set clear toggle 579 6384D-ATARM-04-May-09 * BCPC: RC Compare Effect on TIOB BCPC 0 0 1 1 0 1 0 1 Effect none set clear toggle * BEEVT: External Event Effect on TIOB BEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle * BSWTRG: Software Trigger Effect on TIOB BSWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle 580 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 34.6.6 TC Counter Value Register Register Name:TC_CVx [x=0..2] Access Type:Read-only 31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CV 7 6 5 4 CV 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 * CV: Counter Value CV contains the counter value in real time. 581 6384D-ATARM-04-May-09 34.6.7 TC Register A Register Name:TC_RAx [x=0..2] Access Type:Read-only if WAVE = 0, Read-write if WAVE = 1 31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RA 7 6 5 4 RA 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 * RA: Register A RA contains the Register A value in real time. 582 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 34.6.8 TC Register B Register Name:TC_RBx [x=0..2] Access Type:Read-only if WAVE = 0, Read-write if WAVE = 1 31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RB 7 6 5 4 RB 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 * RB: Register B RB contains the Register B value in real time. 34.6.9 TC Register C Register Name:TC_RCx [x=0..2] Access Type:Read-write 31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RC 7 6 5 4 RC 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 * RC: Register C RC contains the Register C value in real time. 583 6384D-ATARM-04-May-09 34.6.10 TC Status Register Register Name:TC_SRx [x=0..2] Access Type:Read-only 31 - 23 - 15 - 7 ETRGS 30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 MTIOB 10 - 2 CPAS 25 - 17 MTIOA 9 - 1 LOVRS 24 - 16 CLKSTA 8 - 0 COVFS * COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. * LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. * CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. * CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. * CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. * LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. * LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. * ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. 584 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. * MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. * MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. 585 6384D-ATARM-04-May-09 34.6.11 TC Interrupt Enable Register Register Name:TC_IERx [x=0..2] Access Type:Write-only 31 - 23 - 15 - 7 ETRGS 30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS * COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. * LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt. * CPAS: RA Compare 0 = No effect. 1 = Enables the RA Compare Interrupt. * CPBS: RB Compare 0 = No effect. 1 = Enables the RB Compare Interrupt. * CPCS: RC Compare 0 = No effect. 1 = Enables the RC Compare Interrupt. * LDRAS: RA Loading 0 = No effect. 1 = Enables the RA Load Interrupt. * LDRBS: RB Loading 0 = No effect. 1 = Enables the RB Load Interrupt. * ETRGS: External Trigger 0 = No effect. 1 = Enables the External Trigger Interrupt. 586 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 34.6.12 TC Interrupt Disable Register Register Name:TC_IDRx [x=0..2] Access Type:Write-only 31 - 23 - 15 - 7 ETRGS 30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS * COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. * LOVRS: Load Overrun 0 = No effect. 1 = Disables the Load Overrun Interrupt (if WAVE = 0). * CPAS: RA Compare 0 = No effect. 1 = Disables the RA Compare Interrupt (if WAVE = 1). * CPBS: RB Compare 0 = No effect. 1 = Disables the RB Compare Interrupt (if WAVE = 1). * CPCS: RC Compare 0 = No effect. 1 = Disables the RC Compare Interrupt. * LDRAS: RA Loading 0 = No effect. 1 = Disables the RA Load Interrupt (if WAVE = 0). * LDRBS: RB Loading 0 = No effect. 1 = Disables the RB Load Interrupt (if WAVE = 0). * ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt. 587 6384D-ATARM-04-May-09 34.6.13 TC Interrupt Mask Register Register Name:TC_IMRx [x=0..2] Access Type:Read-only 31 - 23 - 15 - 7 ETRGS 30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS * COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled. * LOVRS: Load Overrun 0 = The Load Overrun Interrupt is disabled. 1 = The Load Overrun Interrupt is enabled. * CPAS: RA Compare 0 = The RA Compare Interrupt is disabled. 1 = The RA Compare Interrupt is enabled. * CPBS: RB Compare 0 = The RB Compare Interrupt is disabled. 1 = The RB Compare Interrupt is enabled. * CPCS: RC Compare 0 = The RC Compare Interrupt is disabled. 1 = The RC Compare Interrupt is enabled. * LDRAS: RA Loading 0 = The Load RA Interrupt is disabled. 1 = The Load RA Interrupt is enabled. * LDRBS: RB Loading 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled. * ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled. 588 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 35. MultiMedia Card Interface (MCI) 35.1 Overview The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V3.11, the SDIO Specification V1.1 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral DMA Controller (PDC) channels, minimizing processor intervention for large buffer transfers. The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 2 slot(s). Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology. 589 6384D-ATARM-04-May-09 35.2 Block Diagram Figure 35-1. Block Diagram APB Bridge PDC APB MCCK(1) MCCDA(1) MCDA0(1) PMC MCK MCDA1(1) MCDA2(1) MCDA3(1) MCI Interface PIO MCCDB(1) MCDB0(1) MCDB1(1) MCDB2(1) Interrupt Control MCDB3(1) MCI Interrupt Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB,MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. 590 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 35.3 Application Block Diagram Figure 35-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer MCI Interface 1 2 3 4 5 6 78 1234567 MMC 9 SDCard 35.4 Pin Name List I/O Lines Description Pin Description Command/response Clock Data 0..3 of Slot A Data 0..3 of Slot B Type(1) I/O/PP/OD I/O I/O/PP I/O/PP Comments CMD of an MMC or SDCard/SDIO CLK of an MMC or SD Card/SDIO DAT0 of an MMC DAT[0..3] of an SD Card/SDIO DAT0 of an MMC DAT[0..3] of an SD Card/SDIO Table 35-1. Pin Name(2) MCCDA/MCCDB MCCK MCDA0 - MCDA3 MCDB0 - MCDB3 Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. 35.5 35.5.1 Product Dependencies I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins. 35.5.2 Power Management The MCI may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the MCI clock. 591 6384D-ATARM-04-May-09 35.5.3 Interrupt The MCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the MCI interrupt requires programming the AIC before configuring the MCI. 35.6 Bus Topology Figure 35-3. Multimedia Memory Card Bus Topology 1234567 MMC The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines. Table 35-2. Pin Number 1 2 3 4 5 6 7 Notes: Bus Topology Name RSV CMD VSS1 VDD CLK VSS2 DAT[0] Type NC I/O/PP/OD S S I/O S I/O/PP (1) Description Not connected Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data 0 MCI Pin Name(2) (Slot z) MCCDz VSS VDD MCCK VSS MCDz0 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. Figure 35-4. MMC Bus Connections (One Slot) MCI MCDA0 MCCDA MCCK 1234567 MMC1 1234567 MMC2 1234567 MMC3 Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. 592 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 35-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 35-3. Table 35-3. Pin Number 1 2 3 4 5 6 7 8 9 Notes: SD Memory Card Bus Signals Name CD/DAT[3] CMD VSS1 VDD CLK VSS2 DAT[0] DAT[1] DAT[2] Type(1) I/O/PP PP S S I/O S I/O/PP I/O/PP I/O/PP Description Card detect/ Data line Bit 3 Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data line Bit 0 Data line Bit 1 or Interrupt Data line Bit 2 MCI Pin Name(2) (Slot z) MCDz3 MCCDz VSS VDD MCCK VSS MCDz0 MCDz1 MCDz2 1. I: input, O: output, PP: Push Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. Figure 35-6. SD Card Bus Connections with One Slot MCDA0 - MCDA3 MCCK MCCDA 1 2 3 4 5 6 78 SD CARD Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. 9 593 6384D-ATARM-04-May-09 Figure 35-7. SD Card Bus Connections with Two Slots MCDA0 - MCDA3 MCCK MCCDA 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1234567 MMC1 1 2 3 4 5 6 78 SD CARD 1 MCDB0 - MCDB3 MCCDB Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK,MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. Figure 35-8. Mixing MultiMedia and SD Memory Cards with Two Slots MCDA0 MCCDA MCCK 1234567 MMC2 9 9 SD CARD 2 1234567 MMC3 MCDB0 - MCDB3 SD CARD MCCDB Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the MCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs. 594 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 9 AT91SAM9G20 Preliminary 35.7 MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: * Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. * Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line. * Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. See also Table 35-5 on page 596. MultiMediaCard bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock MCI Clock. Two types of data transfer commands are defined: * Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. * Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a pre-defined block count (See "Data Transfer Operation" on page 597.). The MCI provides a set of registers to perform the entire range of MultiMedia Card operations. 35.7.1 Command - Response Operation After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR Control Register. The PWSEN bit saves power by dividing the MCI clock by 2PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the MCI Mode Register (MCI_MR) allow stopping the MCI Clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. The command and the response of the card are clocked out with the rising edge of the MCI Clock. All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification. 595 6384D-ATARM-04-May-09 The two bus modes (open drain and push/pull) needed to process all the operations are defined in the MCI command register. The MCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: Table 35-4. Host Command CMD S T Content CRC E Z NID Cycles ****** Z S T CID Content Z Z Z The command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Register are described in Table 35-5 and Table 35-6. Table 35-5. CMD Index CMD2 ALL_SEND_CID Command Description Type bcr Argument [31:0] stuff bits Resp R2 Abbreviation ALL_SEND_CID Command Description Asks all cards to send their CID numbers on the CMD line Note: bcr means broadcast command with response. Table 35-6. Field Fields and Values for MCI_CMDR Command Register Value 2 (CMD2) 2 (R2: 136 bits response) 0 (not a special command) 1 0 (NID cycles ==> 5 cycles) 0 (No transfer) X (available only in transfer command) X (available only in transfer command) 0 (not a special command) CMDNB (command number) RSPTYP (response type) SPCMD (special command) OPCMD (open drain command) MAXLAT (max latency for command to response) TRCMD (transfer command) TRDIR (transfer direction) TRTYP (transfer type) IOSPCMD (SDIO special command) The MCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps: * Fill the argument register (MCI_ARGR) with the command argument. * Set the command register (MCI_CMDR) (see Table 35-6). The command is sent immediately after writing the command register. The status bit CMDRDY in the status register (MCI_SR) is asserted when the command is completed. If the command requires a response, it can be read in the MCI response register (MCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (MCI_IER) allows using an interrupt method. 596 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 35-9. Command/Response Functional Flow Diagram Set the command argument MCI_ARGR = Argument(1) Set the command MCI_CMDR = Command Read MCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? Read response if required RETURN ERROR(1) RETURN OK Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMedia Card specification). 35.7.2 Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI Command Register (MCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length (BLKLEN field) must be defined either in the mode register MCI_MR, or in the Block Register MCI_BLKR. This field determines the size of the data block. Enabling PDC Force Byte Transfer (PDCFBYTE bit in the MCI_MR) allows the PDC to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. When PDC Force Byte Transfer is disabled, the PDC type of transfers are in words, otherwise the type of transfers are in bytes. 597 6384D-ATARM-04-May-09 Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): * Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received. * Multiple block read (or write) with pre-defined block count (since version 3.1 and higher): The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the MCI Block Register (MCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer. 35.7.3 Read Operation The following flowchart shows how to read a single block with or without use of PDC facilities. In this example (see Figure 35-10), a polling method is used to wait for the end of read. Similarly, the user can configure the interrupt enable register (MCI_IER) to trigger an interrupt at the end of read. 598 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 35-10. Read Functional Flow Diagram Send SELECT/DESELECT_CARD command(1) to select the card (1) Send SET_BLOCKLEN command No Read with PDC Yes Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght <<16)(2) Set the block count (if necessary) MCI_BLKR |= (BlockCount << 0) Set the PDCMODE bit MCI_MR |= PDCMODE Set the block length (in bytes) (2) MCI_MR |= (BlockLength << 16) Set the block count (if necessary) MCI_BLKR |= (BlockCount << 0) Send READ_SINGLE_BLOCK command(1) Configure the PDC channel MCI_RPR = Data Buffer Address MCI_RCR = BlockLength/4 MCI_PTCR = RXTEN Number of words to read = BlockLength/4 Send READ_SINGLE_BLOCK command(1) Yes Number of words to read = 0 ? Read status register MCI_SR No Read status register MCI_SR Poll the bit ENDRX = 0? Yes Poll the bit RXRDY = 0? Yes No No Read data = MCI_RDR Number of words to read = Number of words to read -1 RETURN RETURN Note: 1. It is assumed that this command has been correctly sent (see Figure 35-9). 2. This field is also accessible in the MCI Block Register (MCI_BLKR). 599 6384D-ATARM-04-May-09 35.7.4 Write Operation In write operation, the MCI Mode Register (MCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PDCPADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit PDCMODE enables PDC transfer. The following flowchart shows how to write a single block with or without use of PDC facilities (see Figure 35-11). Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (MCI_IMR). 600 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 35-11. Write Functional Flow Diagram Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command(1) No Write using PDC Yes Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght <<16)(2) Set the block count (if necessary) MCI_BLKR |= (BlockCount << 0) Set the PDCMODE bit MCI_MR |= PDCMODE Set the block length (in bytes) (2) MCI_MR |= (BlockLength << 16) Set the block count (if necessary) MCI_BLKR |= (BlockCount << 0) Send WRITE_SINGLE_BLOCK command(1) Configure the PDC channel MCI_TPR = Data Buffer Address to write MCI_TCR = BlockLength/4 Number of words to write = BlockLength/4 Send WRITE_SINGLE_BLOCK command(1) MCI_PTCR = TXTEN Yes Number of words to write = 0 ? Read status register MCI_SR No Read status register MCI_SR Poll the bit NOTBUSY= 0? Poll the bit TXRDY = 0? Yes No Yes No MCI_TDR = Data to write Number of words to write = Number of words to write -1 RETURN RETURN Notes: 1. It is assumed that this command has been correctly sent (see Figure 35-9). 2. This field is also accessible in the MCI Block Register (MCI_BLKR). 601 6384D-ATARM-04-May-09 The following flowchart shows how to manage a multiple write block transfer with the PDC (see Figure 35-12). Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (MCI_IMR). Figure 35-12. Multiple Write Functional Flow Diagram Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command (1) Set the PDCMODE bit MCI_MR |= PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLength << 16)(2) Set the block count (if necessary) MCI_BLKR |= (BlockCount << 0) Configure the PDC channel MCI_TPR = Data Buffer Address to write MCI_TCR = BlockLength/4 Send WRITE_MULTIPLE_BLOCK command(1) MCI_PTCR = TXTEN Read status register MCI_SR Poll the bit BLKE = 0? Yes No Send STOP_TRANSMISSION command(1) Poll the bit NOTBUSY = 0? Yes No RETURN Notes: 1. It is assumed that this command has been correctly sent (see Figure 35-9). 2. This field is also accessible in the MCI Block Register (MCI_BLKR). 602 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 35.8 SD/SDIO Card Operations The MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the Multi Media Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features. The physical form factor, pin assignment and data transfer protocol are forward-compatible with the MultiMedia Card with some additions. SD slots can actually be used for more than flash memory cards. Devices that support SDIO can use small devices designed for the SD form factor, such as GPS receivers, Wi-Fi or Bluetooth adapters, modems, barcode readers, IrDA adapters, FM radio tuners, RFID readers, digital cameras and more. SD/SDIO is covered by numerous patents and trademarks, and licensing is only available through the Secure Digital Card Association. The SD/SDIO Card communication is based on a 9-pin interface (Clock, Command, 4 x Data and 3 x Power lines). The communication protocol is defined as a part of this specification. The main difference between the SD/SDIO Card and the MultiMedia Card is the initialization process. The SD/SDIO Card Register (MCI_SDCR) allows selection of the Card Slot and the data bus width. The SD/SDIO Card bus allows dynamic configuration of the number of data lines. After power up, by default, the SD/SDIO Card uses only DAT0 for data transfer. After initialization, the host can change the bus width (number of active data lines). 35.8.1 SDIO Data Transfer Type SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format (1 to 511 blocks), while the SD memory cards are fixed in the block transfer mode. The TRTYP field in the MCI Command Register (MCI_CMDR) allows to choose between SDIO Byte or SDIO Block transfer. The number of bytes/blocks to transfer is set through the BCNT field in the MCI Block Register (MCI_BLKR). In SDIO Block mode, the field BLKLEN must be set to the data block size while this field is not used in SDIO Byte mode. An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share access to the SD bus. In order to allow the sharing of access to the host among multiple devices, SDIO and combo cards can implement the optional concept of suspend/resume (Refer to the SDIO Specification for more details). To send a suspend or a resume command, the host must set the SDIO Special Command field (IOSPCMD) in the MCI Command Register. 35.8.2 SDIO Interrupts Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the DAT[1] line to signal the card's interrupt to the host. An SDIO interrupt on each slot can be enabled through the MCI Interrupt Enable Register. The SDIO interrupt is sampled regardless of the currently selected slot. 603 6384D-ATARM-04-May-09 35.9 MultiMedia Card Interface (MCI) User Interface Register Mapping Register Control Register Mode Register Data Timeout Register SD/SDIO Card Register Argument Register Command Register Block Register Reserved Response Register (1) (1) (1) Table 35-7. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 Name MCI_CR MCI_MR MCI_DTOR MCI_SDCR MCI_ARGR MCI_CMDR MCI_BLKR - MCI_RSPR MCI_RSPR MCI_RSPR MCI_RSPR MCI_RDR MCI_TDR - MCI_SR MCI_IER MCI_IDR MCI_IMR - - Access Write-only Read-write Read-write Read-write Read-write Write-only Read-write - Read-only Read-only Read-only Read-only Read-only Write-only - Read-only Write-only Write-only Read-only - - Reset - 0x0 0x0 0x0 0x0 - 0x0 - 0x0 0x0 0x0 0x0 0x0 - - 0xC0E5 - - 0x0 - - Response Register Response Register Response Register(1) Receive Data Register Transmit Data Register Reserved Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for the PDC 0x38 - 0x3C 0x40 0x44 0x48 0x4C 0x50-0xFC 0x100-0x124 Note: 1. The response register can be read by N accesses at the same MCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response. 604 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 35.9.1 Name: MCI Control Register MCI_CR Access Type: Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SWRST - - - PWSDIS PWSEN MCIDIS MCIEN * MCIEN: Multi-Media Interface Enable 0 = No effect. 1 = Enables the Multi-Media Interface if MCDIS is 0. * MCIDIS: Multi-Media Interface Disable 0 = No effect. 1 = Disables the Multi-Media Interface. * PWSEN: Power Save Mode Enable 0 = No effect. 1 = Enables the Power Saving Mode if PWSDIS is 0. Warning: Before enabling this mode, the user must set a value different from 0 in the PWSDIV field (Mode Register MCI_MR). * PWSDIS: Power Save Mode Disable 0 = No effect. 1 = Disables the Power Saving Mode. * SWRST: Software Reset 0 = No effect. 1 = Resets the MCI. A software triggered hardware reset of the MCI interface is performed. 605 6384D-ATARM-04-May-09 35.9.2 Name: MCI Mode Register MCI_MR Access Type: Read-write 31 30 29 28 27 26 25 24 BLKLEN 23 22 21 20 19 18 17 16 BLKLEN 15 14 13 12 11 10 9 8 PDCMODE 7 PDCPADV 6 PDCFBYTE 5 WRPROOF 4 RDPROOF 3 2 PWSDIV 1 0 CLKDIV * CLKDIV: Clock Divider Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)). * PWSDIV: Power Saving Divider Multimedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode. Warning: This value must be different from 0 before enabling the Power Save Mode in the MCI_CR (MCI_PWSEN bit). * RDPROOF Read Proof Enable Enabling Read Proof allows to stop the MCI Clock during read access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. 0 = Disables Read Proof. 1 = Enables Read Proof. * WRPROOF Write Proof Enable Enabling Write Proof allows to stop the MCI Clock during write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. 0 = Disables Write Proof. 1 = Enables Write Proof. * PDCFBYTE: PDC Force Byte Transfer Enabling PDC Force Byte Transfer allows the PDC to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. Warning: BLKLEN value depends on PDCFBYTE. 0 = Disables PDC Force Byte Transfer. PDC type of transfer are in words. 1 = Enables PDC Force Byte Transfer. PDC type of transfer are in bytes. * PDCPADV: PDC Padding Value 0 = 0x00 value is used when padding data in write transfer (not only PDC transfer). 1 = 0xFF value is used when padding data in write transfer (not only PDC transfer). 606 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * PDCMODE: PDC-oriented Mode 0 = Disables PDC transfer 1 = Enables PDC transfer. In this case, UNRE and OVRE flags in the MCI Mode Register (MCI_SR) are deactivated after the PDC transfer has been completed. * BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the MCI Block Register (MCI_BLKR). Bits 16 and 17 must be set to 0 if PDCFBYTE is disabled. Note: In SDIO Byte mode, BLKLEN field is not used. 607 6384D-ATARM-04-May-09 35.9.3 Name: MCI Data Timeout Register MCI_DTOR Access Type: Read-write 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - DTOMUL DTOCYC * DTOCYC: Data Timeout Cycle Number * DTOMUL: Data Timeout Multiplier These fields determine the maximum number of Master Clock cycles that the MCI waits between two data block transfers. It equals (DTOCYC x Multiplier). Multiplier is defined by DTOMUL as shown in the following table: DTOMUL 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Multiplier 1 16 128 256 1024 4096 65536 1048576 If the data time-out set by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error flag (DTOE) in the MCI Status Register (MCI_SR) raises. 608 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 35.9.4 Name: MCI SDCard/SDIO Register MCI_SDCR Access Type: Read-write 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SDCBUS - - - - - SDCSEL * SDCSEL: SDCard/SDIO Slot SDCSEL 0 0 1 1 0 1 0 1 SDCard/SDIO Slot Slot A is selected. Slot B selected Reserved Reserved * SDCBUS: SDCard/SDIO Bus Width 0 = 1-bit data bus 1 = 4-bit data bus 609 6384D-ATARM-04-May-09 35.9.5 Name: MCI Argument Register MCI_ARGR Access Type: Read-write 31 30 29 28 27 26 25 24 ARG 23 22 21 20 19 18 17 16 ARG 15 14 13 12 11 10 9 8 ARG 7 6 5 4 3 2 1 0 ARG * ARG: Command Argument 610 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 35.9.6 Name: MCI Command Register MCI_CMDR Access Type: Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 17 IOSPCMD 16 - 15 - 14 13 TRTYP 12 11 TRDIR 10 9 TRCMD 8 - 7 - 6 - 5 MAXLAT 4 OPDCMD 3 2 SPCMD 1 0 RSPTYP CMDNB This register is write-protected while CMDRDY is 0 in MCI_SR. If an Interrupt command is sent, this register is only writeable by an interrupt response (field SPCMD). This means that the current command execution cannot be interrupted or modified. * CMDNB: Command Number * RSPTYP: Response Type RSP 0 0 1 1 0 1 0 1 Response Type No response. 48-bit response. 136-bit response. Reserved. * SPCMD: Special Command SPCMD 0 0 0 0 0 1 Command Not a special CMD. Initialization CMD: 74 clock cycles for initialization sequence. Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. Reserved. Interrupt command: Corresponds to the Interrupt Mode (CMD40). Interrupt response: Corresponds to the Interrupt Mode (CMD40). 0 0 1 1 1 1 0 0 0 1 0 1 * OPDCMD: Open Drain Command 0 = Push pull command 1 = Open drain command 611 6384D-ATARM-04-May-09 * MAXLAT: Max Latency for Command to Response 0 = 5-cycle max latency 1 = 64-cycle max latency * TRCMD: Transfer Command TRCMD 0 0 1 1 0 1 0 1 Transfer Type No data transfer Start data transfer Stop data transfer Reserved * TRDIR: Transfer Direction 0 = Write 1 = Read * TRTYP: Transfer Type TRTYP 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Transfer Type MMC/SDCard Single Block MMC/SDCard Multiple Block MMC Stream Reserved SDIO Byte SDIO Block Reserved Reserved * IOSPCMD: SDIO Special Command IOSPCMD 0 0 1 1 0 1 0 1 SDIO Special Command Type Not a SDIO Special Command SDIO Suspend Command SDIO Resume Command Reserved 612 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 35.9.7 Name: MCI Block Register MCI_BLKR Access Type: Read-write 31 30 29 28 27 26 25 24 BLKLEN 23 22 21 20 19 18 17 16 BLKLEN 15 14 13 12 11 10 9 8 BCNT 7 6 5 4 3 2 1 0 BCNT * BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer. The transfer data type and the authorized values for BCNT field are determined by the TRTYP field in the MCI Command Register (MCI_CMDR): TRTYP 0 1 1 0 0 0 Other values 1 0 1 Type of Transfer MMC/SDCard Multiple Block SDIO Byte SDIO Block BCNT Authorized Values From 1 to 65535: Value 0 corresponds to an infinite block transfer. From 1 to 512 bytes: value 0 corresponds to a 512-byte transfer. Values from 0x200 to 0xFFFF are forbidden. From 1 to 511 blocks: value 0 corresponds to an infinite block transfer. Values from 0x200 to 0xFFFF are forbidden. Reserved. Warning: In SDIO Byte and Block modes, writing to the 7 last bits of BCNT field, is forbidden and may lead to unpredictable results. * BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the MCI Mode Register (MCI_MR). Bits 16 and 17 must be set to 0 if PDCFBYTE is disabled. Note: In SDIO Byte mode, BLKLEN field is not used. 613 6384D-ATARM-04-May-09 35.9.8 Name: MCI Response Register MCI_RSPR Access Type: Read-only 31 30 29 28 27 26 25 24 RSP 23 22 21 20 19 18 17 16 RSP 15 14 13 12 11 10 9 8 RSP 7 6 5 4 3 2 1 0 RSP * RSP: Response Note: 1. The response register can be read by N accesses at the same MCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response. 614 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 35.9.9 Name: MCI Receive Data Register MCI_RDR Access Type: Read-only 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 7 6 5 4 3 2 1 0 DATA * DATA: Data to Read 615 6384D-ATARM-04-May-09 35.9.10 Name: MCI Transmit Data Register MCI_TDR Access Type: Write-only 31 30 29 28 27 26 25 24 DATA 23 22 21 20 19 18 17 16 DATA 15 14 13 12 11 10 9 8 DATA 7 6 5 4 3 2 1 0 DATA * DATA: Data to Write 616 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 35.9.11 Name: MCI Status Register MCI_SR Access Type: Read-only 31 30 29 28 27 26 25 24 UNRE 23 OVRE 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 DTOE 14 DCRCE 13 RTOE 12 RENDE 11 RCRCE 10 RDIRE 9 RINDE 8 TXBUFE 7 RXBUFF 6 - 5 - 4 3 2 SDIOIRQB 1 SDIOIRQA 0 ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY * CMDRDY: Command Ready 0 = A command is in progress. 1 = The last command has been sent. Cleared when writing in the MCI_CMDR. * RXRDY: Receiver Ready 0 = Data has not yet been received since the last read of MCI_RDR. 1 = Data has been received since the last read of MCI_RDR. * TXRDY: Transmit Ready 0= The last data written in MCI_TDR has not yet been transferred in the Shift Register. 1= The last data written in MCI_TDR has been transferred in the Shift Register. * BLKE: Data Block Ended This flag must be used only for Write Operations. 0 = A data block transfer is not yet finished. Cleared when reading the MCI_SR. 1 = A data block transfer has ended, including the CRC16 Status transmission. In PDC mode (PDCMODE=1), the flag is set when the CRC Status of the last block has been transmitted (TXBUFE already set). Otherwise (PDCMODE=0), the flag is set for each transmitted CRC Status. Refer to the MMC or SD Specification for more details concerning the CRC Status. * DTIP: Data Transfer in Progress 0 = No data transfer in progress. 1 = The current data transfer is still in progress, including CRC16 calculation. Cleared at the end of the CRC16 calculation. * NOTBUSY: MCI Not Busy This flag must be used only for Write Operations. A block write operation uses a simple busy signalling of the write operation duration on the data (DAT0) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line (DAT0) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free. 617 6384D-ATARM-04-May-09 The NOTBUSY flag allows to deal with these different states. 0 = The MCI is not ready for new data transfer. Cleared at the end of the card response. 1 = The MCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card. Refer to the MMC or SD Specification for more details concerning the busy behavior. * ENDRX: End of RX Buffer 0 = The Receive Counter Register has not reached 0 since the last write in MCI_RCR or MCI_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in MCI_RCR or MCI_RNCR. * ENDTX: End of TX Buffer 0 = The Transmit Counter Register has not reached 0 since the last write in MCI_TCR or MCI_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in MCI_TCR or MCI_TNCR. Note: BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines and not only transferred from the PDC to the MCI Controller. * RXBUFF: RX Buffer Full 0 = MCI_RCR or MCI_RNCR has a value other than 0. 1 = Both MCI_RCR and MCI_RNCR have a value of 0. * TXBUFE: TX Buffer Empty 0 = MCI_TCR or MCI_TNCR has a value other than 0. 1 = Both MCI_TCR and MCI_TNCR have a value of 0. Note: BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines and not only transferred from the PDC to the MCI Controller. * RINDE: Response Index Error 0 = No error. 1 = A mismatch is detected between the command index sent and the response index received. Cleared when writing in the MCI_CMDR. * RDIRE: Response Direction Error 0 = No error. 1 = The direction bit from card to host in the response has not been detected. * RCRCE: Response CRC Error 0 = No error. 1 = A CRC7 error has been detected in the response. Cleared when writing in the MCI_CMDR. * RENDE: Response End Bit Error 0 = No error. 1 = The end bit of the response has not been detected. Cleared when writing in the MCI_CMDR. 618 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * RTOE: Response Time-out Error 0 = No error. 1 = The response time-out set by MAXLAT in the MCI_CMDR has been exceeded. Cleared when writing in the MCI_CMDR. * DCRCE: Data CRC Error 0 = No error. 1 = A CRC16 error has been detected in the last data block. Reset by reading in the MCI_SR register. * DTOE: Data Time-out Error 0 = No error. 1 = The data time-out set by DTOCYC and DTOMUL in MCI_DTOR has been exceeded. Reset by reading in the MCI_SR register. * OVRE: Overrun 0 = No error. 1 = At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command. * UNRE: Underrun 0 = No error. 1 = At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer command. * SDIOIRQA: SDIO Interrupt for Slot A 0 = No interrupt detected on SDIO Slot A. 1 = A SDIO Interrupt on Slot A has reached. Cleared when reading the MCI_SR. * SDIOIRQB: SDIO Interrupt for Slot B 0 = No interrupt detected on SDIO Slot B. 1 = A SDIO Interrupt on Slot B has reached. Cleared when reading the MCI_SR. * RXBUFF: RX Buffer Full 0 = MCI_RCR or MCI_RNCR has a value other than 0. 1 = Both MCI_RCR and MCI_RNCR have a value of 0. * TXBUFE: TX Buffer Empty 0 = MCI_TCR or MCI_TNCR has a value other than 0. 1 = Both MCI_TCR and MCI_TNCR have a value of 0. 619 6384D-ATARM-04-May-09 35.9.12 Name: MCI Interrupt Enable Register MCI_IER Access Type: Write-only 31 30 29 28 27 26 25 24 UNRE 23 OVRE 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 DTOE 14 DCRCE 13 RTOE 12 RENDE 11 RCRCE 10 RDIRE 9 RINDE 8 TXBUFE 7 RXBUFF 6 - 5 - 4 3 2 SDIOIRQB 1 SDIOIRQA 0 ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY * CMDRDY: Command Ready Interrupt Enable * RXRDY: Receiver Ready Interrupt Enable * TXRDY: Transmit Ready Interrupt Enable * BLKE: Data Block Ended Interrupt Enable * DTIP: Data Transfer in Progress Interrupt Enable * NOTBUSY: Data Not Busy Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * ENDTX: End of Transmit Buffer Interrupt Enable * SDIOIRQA: SDIO Interrupt for Slot A Interrupt Enable * SDIOIRQB: SDIO Interrupt for Slot B Interrupt Enable * RXBUFF: Receive Buffer Full Interrupt Enable * TXBUFE: Transmit Buffer Empty Interrupt Enable * RINDE: Response Index Error Interrupt Enable * RDIRE: Response Direction Error Interrupt Enable * RCRCE: Response CRC Error Interrupt Enable * RENDE: Response End Bit Error Interrupt Enable * RTOE: Response Time-out Error Interrupt Enable * DCRCE: Data CRC Error Interrupt Enable * DTOE: Data Time-out Error Interrupt Enable * OVRE: Overrun Interrupt Enable * UNRE: UnderRun Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 620 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 35.9.13 Name: MCI Interrupt Disable Register MCI_IDR Access Type: Write-only 31 30 29 28 27 26 25 24 UNRE 23 OVRE 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 DTOE 14 DCRCE 13 RTOE 12 RENDE 11 RCRCE 10 RDIRE 9 RINDE 8 TXBUFE 7 RXBUFF 6 - 5 - 4 3 2 SDIOIRQB 1 SDIOIRQA 0 ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY * CMDRDY: Command Ready Interrupt Disable * RXRDY: Receiver Ready Interrupt Disable * TXRDY: Transmit Ready Interrupt Disable * BLKE: Data Block Ended Interrupt Disable * DTIP: Data Transfer in Progress Interrupt Disable * NOTBUSY: Data Not Busy Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * ENDTX: End of Transmit Buffer Interrupt Disable * SDIOIRQA: SDIO Interrupt for Slot A Interrupt Disable * SDIOIRQB: SDIO Interrupt for Slot B Interrupt Disable * RXBUFF: Receive Buffer Full Interrupt Disable * TXBUFE: Transmit Buffer Empty Interrupt Disable * RINDE: Response Index Error Interrupt Disable * RDIRE: Response Direction Error Interrupt Disable * RCRCE: Response CRC Error Interrupt Disable * RENDE: Response End Bit Error Interrupt Disable * RTOE: Response Time-out Error Interrupt Disable * DCRCE: Data CRC Error Interrupt Disable * DTOE: Data Time-out Error Interrupt Disable * OVRE: Overrun Interrupt Disable * UNRE: UnderRun Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 621 6384D-ATARM-04-May-09 35.9.14 Name: MCI Interrupt Mask Register MCI_IMR Access Type: Read-only 31 30 29 28 27 26 25 24 UNRE 23 OVRE 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 DTOE 14 DCRCE 13 RTOE 12 RENDE 11 RCRCE 10 RDIRE 9 RINDE 8 TXBUFE 7 RXBUFF 6 - 5 - 4 3 2 SDIOIRQB 1 SDIOIRQA 0 ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY * CMDRDY: Command Ready Interrupt Mask * RXRDY: Receiver Ready Interrupt Mask * TXRDY: Transmit Ready Interrupt Mask * BLKE: Data Block Ended Interrupt Mask * DTIP: Data Transfer in Progress Interrupt Mask * NOTBUSY: Data Not Busy Interrupt Mask * ENDRX: End of Receive Buffer Interrupt Mask * ENDTX: End of Transmit Buffer Interrupt Mask * SDIOIRQA: SDIO Interrupt for Slot A Interrupt Mask * SDIOIRQB: SDIO Interrupt for Slot B Interrupt Mask * RXBUFF: Receive Buffer Full Interrupt Mask * TXBUFE: Transmit Buffer Empty Interrupt Mask * RINDE: Response Index Error Interrupt Mask * RDIRE: Response Direction Error Interrupt Mask * RCRCE: Response CRC Error Interrupt Mask * RENDE: Response End Bit Error Interrupt Mask * RTOE: Response Time-out Error Interrupt Mask * DCRCE: Data CRC Error Interrupt Mask * DTOE: Data Time-out Error Interrupt Mask * OVRE: Overrun Interrupt Mask * UNRE: UnderRun Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled. 622 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36. Ethernet MAC 10/100 (EMAC) 36.1 Overview The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface. The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal. The statistics register block contains registers for counting various types of event associated with transmit and receive operations. These registers, along with the status words stored in the receive buffer list, enable software to generate network management statistics compatible with IEEE 802.3. 36.2 Block Diagram Figure 36-1. EMAC Block Diagram Address Checker APB Slave Register Interface Statistics Registers MDIO Control Registers DMA Interface RX FIFO TX FIFO Ethernet Receive AHB Master MII/RMII Ethernet Transmit 623 6384D-ATARM-04-May-09 36.3 Functional Description The MACB has several clock domains: * * * System bus clock (AHB and APB): DMA and register blocks Transmit clock: transmit block Receive clock: receive and address checker blocks The only system constraint is 160 MHz for the system bus clock, above which MDC would toggle at above 2.5 MHz. The system bus clock must run at least as fast as the receive clock and transmit clock (25 MHz at 100 Mbps, and 2.5 MHZ at 10 Mbps). Figure 36-1 illustrates the different blocks of the EMAC module. The control registers drive the MDIO interface, setup up DMA activity, start frame transmission and select modes of operation such as full- or half-duplex. The receive block checks for valid preamble, FCS, alignment and length, and presents received frames to the address checking block and DMA interface. The transmit block takes data from the DMA interface, adds preamble and, if necessary, pad and FCS, and transmits data according to the CSMA/CD (carrier sense multiple access with collision detect) protocol. The start of transmission is deferred if CRS (carrier sense) is active. If COL (collision) becomes active during transmission, a jam sequence is asserted and the transmission is retried after a random back off. CRS and COL have no effect in full duplex mode. The DMA block connects to external memory through its AHB bus interface. It contains receive and transmit FIFOs for buffering frame data. It loads the transmit FIFO and empties the receive FIFO using AHB bus master operations. Receive data is not sent to memory until the address checking logic has determined that the frame should be copied. Receive or transmit frames are stored in one or more buffers. Receive buffers have a fixed length of 128 bytes. Transmit buffers range in length between 0 and 2047 bytes, and up to 128 buffers are permitted per frame. The DMA block manages the transmit and receive framebuffer queues. These queues can hold multiple frames. 36.3.1 Clock Synchronization module in the EMAC requires that the bus clock (hclk) runs at the speed of the macb_tx/rx_clk at least, which is 25 MHz at 100 Mbps, and 2.5 MHz at 10 Mbps. 36.3.2 Memory Interface Frame data is transferred to and from the EMAC through the DMA interface. All transfers are 32bit words and may be single accesses or bursts of 2, 3 or 4 words. Burst accesses do not cross sixteen-byte boundaries. Bursts of 4 words are the default data transfer; single accesses or bursts of less than four words may be used to transfer data at the beginning or the end of a buffer. The DMA controller performs six types of operation on the bus. In order of priority, these are: 1. Receive buffer manager write 2. Receive buffer manager read 3. Transmit data DMA read 4. Receive data DMA write 624 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 5. Transmit buffer manager read 6. Transmit buffer manager write 36.3.2.1 FIFO The FIFO depths are 128 bytes for receive and 128 bytes for transmit and are a function of the system clock speed, memory latency and network speed. Data is typically transferred into and out of the FIFOs in bursts of four words. For receive, a bus request is asserted when the FIFO contains four words and has space for 28 more. For transmit, a bus request is generated when there is space for four words, or when there is space for 27 words if the next transfer is to be only one or two words. Thus the bus latency must be less than the time it takes to load the FIFO and transmit or receive three words (112 bytes) of data. At 100 Mbit/s, it takes 8960 ns to transmit or receive 112 bytes of data. In addition, six master clock cycles should be allowed for data to be loaded from the bus and to propagate through the FIFOs. For a 133 MHz master clock this takes 45 ns, making the bus latency requirement 8915 ns. 36.3.2.2 Receive Buffers Received frames, including CRC/FCS optionally, are written to receive buffers stored in memory. Each receive buffer is 128 bytes long. The start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. The receive buffer start location is a word address. For the first buffer of a frame, the start location can be offset by up to three bytes depending on the value written to bits 14 and 15 of the network configuration register. If the start location of the buffer is offset the available length of the first buffer of a frame is reduced by the corresponding number of bytes. Each list entry consists of two words, the first being the address of the receive buffer and the second being the receive status. If the length of a receive frame exceeds the buffer length, the status word for the used buffer is written with zeroes except for the "start of frame" bit and the offset bits, if appropriate. Bit zero of the address field is written to one to show the buffer has been used. The receive buffer manager then reads the location of the next receive buffer and fills that with receive frame data. The final buffer descriptor status word contains the complete frame status. Refer to Table 36-1 for details of the receive buffer descriptor list. Table 36-1. Bit Receive Buffer Descriptor Entry Function Word 0 31:2 1 0 Address of beginning of buffer Wrap - marks last descriptor in receive buffer descriptor list. Ownership - needs to be zero for the EMAC to write data to the receive buffer. The EMAC sets this to one once it has successfully written a frame to memory. Software has to clear this bit before the buffer can be used again. Word 1 31 30 29 Global all ones broadcast address detected Multicast hash match Unicast hash match 625 6384D-ATARM-04-May-09 Table 36-1. Bit 28 27 26 25 24 23 22 21 20 19:17 16 15 14 Receive Buffer Descriptor Entry (Continued) Function External address match Reserved for future use Specific address register 1 match Specific address register 2 match Specific address register 3 match Specific address register 4 match Type ID match VLAN tag detected (i.e., type id of 0x8100) Priority tag detected (i.e., type id of 0x8100 and null VLAN identifier) VLAN priority (only valid if bit 21 is set) Concatenation format indicator (CFI) bit (only valid if bit 21 is set) End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status are bits 12, 13 and 14. Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a whole frame. Receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address. Updated with the current values of the network configuration register. If jumbo frame mode is enabled through bit 3 of the network configuration register, then bits 13:12 of the receive buffer descriptor entry are used to indicate bits 13:12 of the frame length. Length of frame including FCS (if selected). Bits 13:12 are also used if jumbo frame mode is selected. 13:12 11:0 To receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits 31 to 2 in the first word of each list entry. Bit zero must be written with zero. Bit one is the wrap bit and indicates the last entry in the list. The start location of the receive buffer descriptor list must be written to the receive buffer queue pointer register before setting the receive enable bit in the network control register to enable receive. As soon as the receive block starts writing received frame data to the receive FIFO, the receive buffer manager reads the first receive buffer location pointed to by the receive buffer queue pointer register. If the filter block then indicates that the frame should be copied to memory, the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered. If the current buffer pointer has its wrap bit set or is the 1024th descriptor, the next receive buffer location is read from the beginning of the receive descriptor list. Otherwise, the next receive buffer location is read from the next word in memory. There is an 11-bit counter to count out the 2048 word locations of a maximum length, receive buffer descriptor list. This is added with the value originally written to the receive buffer queue pointer register to produce a pointer into the list. A read of the receive buffer queue pointer register returns the pointer value, which is the queue entry currently being accessed. The counter is reset after receive status is written to a descriptor that has its wrap bit set or rolls over to zero after 1024 descriptors have been accessed. The value written to the receive buffer pointer register may be any word-aligned address, provided that there are at least 2048 word locations available between the pointer and the top of the memory. 626 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Section 3.6 of the AMBA 2.0 specification states that bursts should not cross 1K boundaries. As receive buffer manager writes are bursts of two words, to ensure that this does not occur, it is best to write the pointer register with the least three significant bits set to zero. As receive buffers are used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate used. If a receive error is detected the receive buffer currently being written is recovered. Previous buffers are not recovered. Software should search through the used bits in the buffer descriptors to find out how many frames have been received. It should be checking the start-offrame and end-of-frame bits, and not rely on the value returned by the receive buffer queue pointer register which changes continuously as more buffers are used. For CRC errored frames, excessive length frames or length field mismatched frames, all of which are counted in the statistics registers, it is possible that a frame fragment might be stored in a sequence of receive buffers. Software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set. For a properly working Ethernet system, there should be no excessively long frames or frames greater than 128 bytes with CRC/FCS errors. Collision fragments are less than 128 bytes long. Therefore, it is a rare occurrence to find a frame fragment in a receive buffer. If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the DMA block sets the buffer not available bit in the receive status register and triggers an interrupt. If bit zero is set when the receive buffer manager reads the location of the receive buffer and a frame is being received, the frame is discarded and the receive resource error statistics register is incremented. A receive overrun condition occurs when bus was not granted in time or because HRESP was not OK (bus error). In a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered. The next frame received with an address that is recognized reuses the buffer. If bit 17 of the network configuration register is set, the FCS of received frames shall not be copied to memory. The frame length indicated in the receive status field shall be reduced by four bytes in this case. 36.3.2.3 Transmit Buffer Frames to be transmitted are stored in one or more transmit buffers. Transmit buffers can be between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum length specified in IEEE Standard 802.3. Zero length buffers are allowed. The maximum number of buffers permitted for each transmit frame is 128. The start location for each transmit buffer is stored in memory in a list of transmit buffer descriptors at a location pointed to by the transmit buffer queue pointer register. Each list entry consists of two words, the first being the byte address of the transmit buffer and the second containing the transmit control and status. Frames can be transmitted with or without automatic CRC generation. If CRC is automatically generated, pad is also automatically generated to take frames to a minimum length of 64 bytes. Table 36-2 on page 628 defines an entry in the transmit buffer descriptor list. To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits 31 to 0 in the first word of each list entry. The second transmit buffer descriptor is initialized with control information that indicates the length of the buffer, whether or not it is to be transmitted with CRC and whether the buffer is the last buffer in the frame. 627 6384D-ATARM-04-May-09 After transmission, the control bits are written back to the second word of the first buffer along with the "used" bit and other status information. Bit 31 is the "used" bit which must be zero when the control word is read if transmission is to happen. It is written to one when a frame has been transmitted. Bits 27, 28 and 29 indicate various transmit error conditions. Bit 30 is the "wrap" bit which can be set for any buffer within a frame. If no wrap bit is encountered after 1024 descriptors, the queue pointer rolls over to the start in a similar fashion to the receive queue. The transmit buffer queue pointer register must not be written while transmit is active. If a new value is written to the transmit buffer queue pointer register, the queue pointer resets itself to point to the beginning of the new queue. If transmit is disabled by writing to bit 3 of the network control, the transmit buffer queue pointer register resets to point to the beginning of the transmit queue. Note that disabling receive does not have the same effect on the receive queue pointer. Once the transmit queue is initialized, transmit is activated by writing to bit 9, the Transmit Start bit of the network control register. Transmit is halted when a buffer descriptor with its used bit set is read, or if a transmit error occurs, or by writing to the transmit halt bit of the network control register. (Transmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register.) Rewriting the start bit while transmission is active is allowed. Transmission control is implemented with a Tx_go variable which is readable in the transmit status register at bit location 3. The Tx_go variable is reset when: - transmit is disabled - a buffer descriptor with its ownership bit set is read - a new value is written to the transmit buffer queue pointer register - bit 10, tx_halt, of the network control register is written - there is a transmit error such as too many retries or a transmit underrun. To set tx_go, write to bit 9, tx_start, of the network control register. Transmit halt does not take effect until any ongoing transmit finishes. If a collision occurs during transmission of a multibuffer frame, transmission automatically restarts from the first buffer of the frame. If a "used" bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. Transmission stops, tx_er is asserted and the FCS is bad. If transmission stops due to a transmit error, the transmit queue pointer resets to point to the beginning of the transmit queue. Software needs to re-initialize the transmit queue after a transmit error. If transmission stops due to a "used" bit being read at the start of the frame, the transmission queue pointer is not reset and transmit starts from the same transmit buffer descriptor when the transmit start bit is written Table 36-2. Bit Transmit Buffer Descriptor Entry Function Word 0 31:0 Byte Address of buffer Word 1 628 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 36-2. Bit Transmit Buffer Descriptor Entry (Continued) Function Used. Needs to be zero for the EMAC to read data from the transmit buffer. The EMAC sets this to one for the first buffer of a frame once it has been successfully transmitted. Software has to clear this bit before the buffer can be used again. Note: This bit is only set for the first buffer in a frame unlike receive where all buffers have the Used bit set once used. 31 30 29 28 27 26:17 16 15 14:11 10:0 Wrap. Marks last descriptor in transmit buffer descriptor list. Retry limit exceeded, transmit error detected Transmit underrun, occurs either when hresp is not OK (bus error) or the transmit data could not be fetched in time or when buffers are exhausted in mid frame. Buffers exhausted in mid frame Reserved No CRC. When set, no CRC is appended to the current frame. This bit only needs to be set for the last buffer of a frame. Last buffer. When set, this bit indicates the last buffer in the current frame has been reached. Reserved Length of buffer 36.3.3 Transmit Block This block transmits frames in accordance with the Ethernet IEEE 802.3 CSMA/CD protocol. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO a word at a time. Data is transmitted least significant nibble first. If necessary, padding is added to increase the frame length to 60 bytes. CRC is calculated as a 32-bit polynomial. This is inverted and appended to the end of the frame, taking the frame length to a minimum of 64 bytes. If the No CRC bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor CRC are appended. In full-duplex mode, frames are transmitted immediately. Back-to-back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to de-assert and then starts transmission after the interframe gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retry transmission after the back off time has elapsed. The back-off time is based on an XOR of the 10 least significant bits of the data coming from the transmit FIFO and a 10-bit pseudo random number generator. The number of bits used depends on the number of collisions seen. After the first collision, 1 bit is used, after the second 2, and so on up to 10. Above 10, all 10 bits are used. An error is indicated and no further attempts are made if 16 attempts cause collisions. If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion and the tx_er signal is asserted. For a properly configured system, this should never happen. If the back pressure bit is set in the network control register in half duplex mode, the transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit-rate mode 64 1s, whenever it sees an incoming frame to force a collision. This provides a way of implementing flow control in half-duplex mode. 629 6384D-ATARM-04-May-09 36.3.4 Pause Frame Support The start of an 802.3 pause frame is as follows: Table 36-3. Start of an 802.3 Pause Frame Source Address 6 bytes Type (Mac Control Frame) 0x8808 Pause Opcode 0x0001 Pause Time 2 bytes Destination Address 0x0180C2000001 The network configuration register contains a receive pause enable bit (13). If a valid pause frame is received, the pause time register is updated with the frame's pause time, regardless of its current contents and regardless of the state of the configuration register bit 13. An interrupt (12) is triggered when a pause frame is received, assuming it is enabled in the interrupt mask register. If bit 13 is set in the network configuration register and the value of the pause time register is non-zero, no new frame is transmitted until the pause time register has decremented to zero. The loading of a new pause time, and hence the pausing of transmission, only occurs when the EMAC is configured for full-duplex operation. If the EMAC is configured for half-duplex, there is no transmission pause, but the pause frame received interrupt is still triggered. A valid pause frame is defined as having a destination address that matches either the address stored in specific address register 1 or matches 0x0180C2000001 and has the MAC control frame type ID of 0x8808 and the pause opcode of 0x0001. Pause frames that have FCS or other errors are treated as invalid and are discarded. Valid pause frames received increment the Pause Frame Received statistic register. The pause time register decrements every 512 bit times (i.e., 128 rx_clks in nibble mode) once transmission has stopped. For test purposes, the register decrements every rx_clk cycle once transmission has stopped if bit 12 (retry test) is set in the network configuration register. If the pause enable bit (13) is not set in the network configuration register, then the decrementing occurs regardless of whether transmission has stopped or not. An interrupt (13) is asserted whenever the pause time register decrements to zero (assuming it is enabled in the interrupt mask register). 36.3.5 Receive Block The receive block checks for valid preamble, FCS, alignment and length, presents received frames to the DMA block and stores the frames destination address for use by the address checking block. If, during frame reception, the frame is found to be too long or rx_er is asserted, a bad frame indication is sent to the DMA block. The DMA block then ceases sending data to memory. At the end of frame reception, the receive block indicates to the DMA block whether the frame is good or bad. The DMA block recovers the current receive buffer if the frame was bad. The receive block signals the register block to increment the alignment error, the CRC (FCS) error, the short frame, long frame, jabber error, the receive symbol error statistics and the length field mismatch statistics. The enable bit for jumbo frames in the network configuration register allows the EMAC to receive jumbo frames of up to 10240 bytes in size. This operation does not form part of the IEEE802.3 specification and is disabled by default. When jumbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded. 630 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.3.6 Address Checking Block The address checking (or filter) block indicates to the DMA block which receive frames should be copied to memory. Whether a frame is copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific address and hash registers and the frame's destination address. In this implementation of the EMAC, the frame's source address is not checked. Provided that bit 18 of the Network Configuration register is not set, a frame is not copied to memory if the EMAC is transmitting in half duplex mode at the time a destination address is received. If bit 18 of the Network Configuration register is set, frames can be received while transmitting in half-duplex mode. Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame make up the destination address. The first bit of the destination address, the LSB of the first byte of the frame, is the group/individual bit: this is One for multicast addresses and Zero for unicast. The All Ones address is the broadcast address, and a special case of multicast. The EMAC supports recognition of four specific addresses. Each specific address requires two registers, specific address register bottom and specific address register top. Specific address register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes. The addresses stored can be specific, group, local or universal. The destination address of received frames is compared against the data stored in the specific address registers once they have been activated. The addresses are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. If a receive frame address matches an active address, the frame is copied to memory. The following example illustrates the use of the address match registers for a MAC address of 21:43:65:87:A9:CB. Preamble 55 SFD D5 DA (Octet0 - LSB) 21 DA(Octet 1) 43 DA(Octet 2) 65 DA(Octet 3) 87 DA(Octet 4) A9 DA (Octet5 - MSB) CB SA (LSB) 00 SA 00 SA 00 SA 00 SA 00 SA (MSB) 43 SA (LSB) 21 631 6384D-ATARM-04-May-09 The sequence above shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom as shown. For a successful match to specific address 1, the following address matching registers must be set up: * Base address + 0x98 0x87654321 (Bottom) * Base address + 0x9C 0x0000CBA9 (Top) And for a successful match to the Type ID register, the following should be set up: * Base address + 0xB8 0x00004321 36.3.7 Broadcast Address The broadcast address of 0xFFFFFFFFFFFF is recognized if the `no broadcast' bit in the network configuration register is zero. Hash Addressing The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in hash register bottom and the most significant bits in hash register top. The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. The destination address is reduced to a 6-bit index into the 64-bit hash register using the following hash function. The hash function is an exclusive or of every sixth bit of the destination address. 36.3.8 hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] da[0] represents the least significant bit of the first byte received, that is, the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received. If the hash index points to a bit that is set in the hash register, then the frame is matched according to whether the frame is multicast or unicast. A multicast match is signalled if the multicast hash enable bit is set. da[0] is 1 and the hash index points to a bit set in the hash register. A unicast match is signalled if the unicast hash enable bit is set. da[0] is 0 and the hash index points to a bit set in the hash register. To receive all multicast frames, the hash register should be set with all ones and the multicast hash enable bit should be set in the network configuration register. 36.3.9 Copy All Frames (or Promiscuous Mode) If the copy all frames bit is set in the network configuration register, then all non-errored frames are copied to memory. For example, frames that are too long, too short, or have FCS errors or 632 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary rx_er asserted during reception are discarded and all others are received. Frames with FCS errors are copied to memory if bit 19 in the network configuration register is set. 36.3.10 Type ID Checking The contents of the type_id register are compared against the length/type ID of received frames (i.e., bytes 13 and 14). Bit 22 in the receive buffer descriptor status is set if there is a match. The reset state of this register is zero which is unlikely to match the length/type ID of any valid Ethernet frame. Note: A type ID match does not affect whether a frame is copied to memory. 36.3.11 VLAN Support An Ethernet encoded 802.1Q VLAN tag looks like this: Table 36-4. 802.1Q VLAN Tag TCI (Tag Control Information) 16 bits First 3 bits priority, then CFI bit, last 12 bits VID TPID (Tag Protocol Identifier) 16 bits 0x8100 The VLAN tag is inserted at the 13th byte of the frame, adding an extra four bytes to the frame. If the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame. The MAC can support frame lengths up to 1536 bytes, 18 bytes more than the original Ethernet maximum frame length of 1518 bytes. This is achieved by setting bit 8 in the network configuration register. The following bits in the receive buffer descriptor status word give information about VLAN tagged frames: * Bit 21 set if receive frame is VLAN tagged (i.e. type id of 0x8100) * Bit 20 set if receive frame is priority tagged (i.e. type id of 0x8100 and null VID). (If bit 20 is set bit 21 is set also.) * Bit 19, 18 and 17 set to priority if bit 21 is set * Bit 16 set to CFI if bit 21 is set 36.3.12 PHY Maintenance The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are configured for the same speed and duplex configuration. The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit two is set in the network status register (about 2000 MCK cycles later when bit ten is set to zero, and bit eleven is set to one in the network configuration register). An interrupt is generated as this bit is set. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. Reading during the shift operation returns the current contents of the shift register. At the end of management operation, the bits have shifted back to their original locations. For a read operation, the data bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bits[31:28] should be written as 0x0011. For a description of MDC generation, see the network configuration register in the "Network Control Register" on page 640. 633 6384D-ATARM-04-May-09 36.3.13 Media Independent Interface The Ethernet MAC is capable of interfacing to both RMII and MII Interfaces. The RMII bit in the EMAC_USRIO register controls the interface that is selected. When this bit is set, the RMII interface is selected, else the MII interface is selected. The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in Table 36-5. Table 36-5. Pin Name Pin Configuration MII ETXCK: Transmit Clock ECRS: Carrier Sense ECOL: Collision Detect ERXDV: Data Valid ERX0 - ERX3: 4-bit Receive Data ERXER: Receive Error ERXCK: Receive Clock ETXEN: Transmit Enable ETX0 - ETX3: 4-bit Transmit Data ETXER: Transmit Error ETXEN: Transmit Enable ETX0 - ETX1: 2-bit Transmit Data ECRSDV: Carrier Sense/Data Valid ERX0 - ERX1: 2-bit Receive Data ERXER: Receive Error RMII EREFCK: Reference Clock ETXCK_EREFCK ECRS ECOL ERXDV ERX0 - ERX3 ERXER ERXCK ETXEN ETX0-ETX3 ETXER The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It uses 2 bits for transmit (ETX0 and ETX1) and two bits for receive (ERX0 and ERX1). There is a Transmit Enable (ETXEN), a Receive Error (ERXER), a Carrier Sense (ECRS_DV), and a 50 MHz Reference Clock (ETXCK_EREFCK) for 100Mb/s data rate. 36.3.13.1 RMII Transmit and Receive Operation The same signals are used internally for both the RMII and the MII operations. The RMII maps these signals in a more pin-efficient manner. The transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. The carrier sense and data valid signals are combined into the ECRSDV signal. This signal contains information on carrier sense, FIFO status, and validity of the data. Transmit error bit (ETXER) and collision detect (ECOL) are not used in RMII mode. 634 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.4 36.4.1 36.4.1.1 Programming Interface Initialization Configuration Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the network control register and network configuration register earlier in this document. To change loop-back mode, the following sequence of operations must be followed: 1. Write to network control register to disable transmit and receive circuits. 2. Write to network control register to change loop-back mode. 3. Write to network control register to re-enable transmit or receive circuits. Note: These writes to network control register cannot be combined in any way. 36.4.1.2 Receive Buffer List Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed in another data structure that also resides in main memory. This data structure (receive buffer queue) is a sequence of descriptor entries as defined in "Receive Buffer Descriptor Entry" on page 625. It points to this data structure. Figure 36-2. Receive Buffer List Receive Buffer 0 Receive Buffer Queue Pointer (MAC Register) Receive Buffer 1 Receive Buffer N Receive Buffer Descriptor List (In memory) (In memory) To create the list of buffers: 1. Allocate a number (n) of buffers of 128 bytes in system memory. 2. Allocate an area 2n words for the receive buffer descriptor entry in system memory and create n entries in this list. Mark all entries in this list as owned by EMAC, i.e., bit 0 of word 0 set to 0. 3. If less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit (bit 1 in word 0 set to 1). 4. Write address of receive buffer descriptor entry to EMAC register receive_buffer queue pointer. 5. The receive circuits can then be enabled by writing to the address recognition registers and then to the network control register. 635 6384D-ATARM-04-May-09 36.4.1.3 Transmit Buffer List Transmit data is read from areas of data (the buffers) in system memory These buffers are listed in another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of descriptor entries (as defined in Table 36-2 on page 628) that points to this data structure. To create this list of buffers: 1. Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. Up to 128 buffers per frame are allowed. 2. Allocate an area 2n words for the transmit buffer descriptor entry in system memory and create N entries in this list. Mark all entries in this list as owned by EMAC, i.e. bit 31 of word 1 set to 0. 3. If fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit -- bit 30 in word 1 set to 1. 4. Write address of transmit buffer descriptor entry to EMAC register transmit_buffer queue pointer. 5. The transmit circuits can then be enabled by writing to the network control register. 36.4.1.4 Address Matching The EMAC register-pair hash address and the four specific address register-pairs must be written with the required values. Each register-pair comprises a bottom register and top register, with the bottom register being written first. The address matching is disabled for a particular register-pair after the bottom-register has been written and re-enabled when the top register is written. See "Address Checking Block" on page 631. for details of address matching. Each register-pair may be written at any time, regardless of whether the receive circuits are enabled or disabled. Interrupts There are 14 interrupt conditions that are detected within the EMAC. These are ORed to make a single interrupt. Depending on the overall system design, this may be passed through a further level of interrupt collection (interrupt controller). On receipt of the interrupt signal, the CPU enters the interrupt handler (Refer to the AIC programmer datasheet). To ascertain which interrupt has been generated, read the interrupt status register. Note that this register clears itself when read. At reset, all interrupts are disabled. To enable an interrupt, write to interrupt enable register with the pertinent interrupt bit set to 1. To disable an interrupt, write to interrupt disable register with the pertinent interrupt bit set to 1. To check whether an interrupt is enabled or disabled, read interrupt mask register: if the bit is set to 1, the interrupt is disabled. 36.4.1.5 36.4.1.6 Transmitting Frames To set up a frame for transmission: 1. Enable transmit in the network control register. 2. Allocate an area of system memory for transmit data. This does not have to be contiguous, varying byte lengths can be used as long as they conclude on byte borders. 3. Set-up the transmit buffer list. 4. Set the network control register to enable transmission and enable interrupts. 5. Write data for transmission into these buffers. 6. Write the address to transmit buffer descriptor queue pointer. 7. Write control and length to word one of the transmit buffer descriptor entry. 636 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 8. Write to the transmit start bit in the network control register. 36.4.1.7 Receiving Frames When a frame is received and the receive circuits are enabled, the EMAC checks the address and, in the following cases, the frame is written to system memory: * if it matches one of the four specific address registers. * if it matches the hash address function. * if it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed. * if the EMAC is configured to copy all frames. The register receive buffer queue pointer points to the next entry (see Table 36-1 on page 625) and the EMAC uses this as the address in system memory to write the frame to. Once the frame has been completely and successfully received and written to system memory, the EMAC then updates the receive buffer descriptor entry with the reason for the address match and marks the area as being owned by software. Once this is complete an interrupt receive complete is set. Software is then responsible for handling the data in the buffer and then releasing the buffer by writing the ownership bit back to 0. If the EMAC is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is set. If there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer not available is set. If the frame is not successfully received, a statistic register is incremented and the frame is discarded without informing software. 637 6384D-ATARM-04-May-09 36.5 Ethernet MAC 10/100 (EMAC) User Interface Register Mapping Register Network Control Register Network Configuration Register Network Status Register Reserved Reserved Transmit Status Register Receive Buffer Queue Pointer Register Transmit Buffer Queue Pointer Register Receive Status Register Interrupt Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Phy Maintenance Register Pause Time Register Pause Frames Received Register Frames Transmitted Ok Register Single Collision Frames Register Multiple Collision Frames Register Frames Received Ok Register Frame Check Sequence Errors Register Alignment Errors Register Deferred Transmission Frames Register Late Collisions Register Excessive Collisions Register Transmit Underrun Errors Register Carrier Sense Errors Register Receive Resource Errors Register Receive Overrun Errors Register Receive Symbol Errors Register Excessive Length Errors Register Receive Jabbers Register Undersize Frames Register SQE Test Errors Register Received Length Field Mismatch Register EMAC_TSR EMAC_RBQP EMAC_TBQP EMAC_RSR EMAC_ISR EMAC_IER EMAC_IDR EMAC_IMR EMAC_MAN EMAC_PTR EMAC_PFR EMAC_FTO EMAC_SCF EMAC_MCF EMAC_FRO EMAC_FCSE EMAC_ALE EMAC_DTF EMAC_LCOL EMAC_ECOL EMAC_TUND EMAC_CSE EMAC_RRE EMAC_ROV EMAC_RSE EMAC_ELE EMAC_RJA EMAC_USF EMAC_STE EMAC_RLE Read-write Read-write Read-write Read-write Read-write Write-only Write-only Read-only Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_3FFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Name EMAC_NCR EMAC_NCFG EMAC_NSR Access Read-write Read-write Read-only Reset 0 0x800 - Table 36-6. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x84 0x88 638 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 36-6. Offset 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xC0 0xC8 - 0xFC Register Mapping (Continued) Register Hash Register Bottom [31:0] Register Hash Register Top [63:32] Register Specific Address 1 Bottom Register Specific Address 1 Top Register Specific Address 2 Bottom Register Specific Address 2 Top Register Specific Address 3 Bottom Register Specific Address 3 Top Register Specific Address 4 Bottom Register Specific Address 4 Top Register Type ID Checking Register User Input/Output Register Reserved Name EMAC_HRB EMAC_HRT EMAC_SA1B EMAC_SA1T EMAC_SA2B EMAC_SA2T EMAC_SA3B EMAC_SA3T EMAC_SA4B EMAC_SA4T EMAC_TID EMAC_USRIO - Access Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write - Reset 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - 639 6384D-ATARM-04-May-09 36.5.1 Network Control Register Register Name: EMAC_NCR Access Type: 31 - 23 - 15 - 7 WESTAT Read-write 30 - 22 - 14 - 6 INCSTAT 29 - 21 - 13 - 5 CLRSTAT 28 - 20 - 12 - 4 MPE 27 - 19 - 11 - 3 TE 26 - 18 - 10 THALT 2 RE 25 - 17 - 9 TSTART 1 LLB 24 - 16 - 8 BP 0 LB * LB: LoopBack Asserts the loopback signal to the PHY. * LLB: Loopback local Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with pclk divided by 4. rx_clk and tx_clk may glitch as the EMAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back. * RE: Receive enable When set, enables the EMAC to receive data. When reset, frame reception stops immediately and the receive FIFO is cleared. The receive queue pointer register is unaffected. * TE: Transmit enable When set, enables the Ethernet transmitter to send data. When reset transmission, stops immediately, the transmit FIFO and control registers are cleared and the transmit queue pointer register resets to point to the start of the transmit descriptor list. * MPE: Management port enable Set to one to enable the management port. When zero, forces MDIO to high impedance state and MDC low. * CLRSTAT: Clear statistics registers This bit is write only. Writing a one clears the statistics registers. * INCSTAT: Increment statistics registers This bit is write only. Writing a one increments all the statistics registers by one for test purposes. * WESTAT: Write enable for statistics registers Setting this bit to one makes the statistics registers writable for functional test purposes. * BP: Back pressure If set in half duplex mode, forces collisions on all received frames. 640 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * TSTART: Start transmission Writing one to this bit starts transmission. * THALT: Transmit halt Writing one to this bit halts transmission as soon as any ongoing frame transmission ends. 641 6384D-ATARM-04-May-09 36.5.2 Network Configuration Register Register Name: EMAC_NCFG Access Type: 31 - 23 - 15 RBOF 7 UNI 6 MTI Read-write 30 - 22 - 14 29 - 21 - 13 PAE 5 NBC 28 - 20 - 12 RTY 4 CAF 27 - 19 IRXFCS 11 CLK 3 JFRAME 2 - 26 - 18 EFRHD 10 25 - 17 DRFCS 9 - 1 FD 24 - 16 RLCE 8 BIG 0 SPD * SPD: Speed Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s. The value of this pin is reflected on the speed pin. * FD: Full Duplex If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin. * CAF: Copy All Frames When set to 1, all valid frames are received. * JFRAME: Jumbo Frames Set to one to enable jumbo frames of up to 10240 bytes to be accepted. * NBC: No Broadcast When set to 1, frames addressed to the broadcast address of all ones are not received. * MTI: Multicast Hash Enable When set, multicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register. * UNI: Unicast Hash Enable When set, unicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register. * BIG: Receive 1536 bytes frames Setting this bit means the EMAC receives frames up to 1536 bytes in length. Normally, the EMAC would reject any frame above 1518 bytes. * CLK: MDC clock divider 642 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5MHz (MDC is only active during MDIO read and write operations). CLK 00 01 10 11 MDC MCK divided by 8 (MCK up to 20 MHz) MCK divided by 16 (MCK up to 40 MHz) MCK divided by 32 (MCK up to 80 MHz) MCK divided by 64 (MCK up to 160 MHz) * RTY: Retry test Must be set to zero for normal operation. If set to one, the back off between collisions is always one slot time. Setting this bit to one helps testing the too many retries condition. Also used in the pause frame tests to reduce the pause counters decrement time from 512 bit times, to every rx_clk cycle. * PAE: Pause Enable When set, transmission pauses when a valid pause frame is received. * RBOF: Receive Buffer Offset Indicates the number of bytes by which the received data is offset from the start of the first receive buffer. RBOF 00 01 10 11 Offset No offset from start of receive buffer One-byte offset from start of receive buffer Two-byte offset from start of receive buffer Three-byte offset from start of receive buffer * RLCE: Receive Length field Checking Enable When set, frames with measured lengths shorter than their length fields are discarded. Frames containing a type ID in bytes 13 and 14 -- length/type ID = 0600 -- are not be counted as length errors. * DRFCS: Discard Receive FCS When set, the FCS field of received frames are not be copied to memory. * EFRHD: Enable Frames to be received in half-duplex mode while transmitting. * IRXFCS: Ignore RX FCS When set, frames with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0. 643 6384D-ATARM-04-May-09 36.5.3 Network Status Register Register Name: EMAC_NSR Access Type: 31 - 23 - 15 - 7 - Read-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 IDLE 25 - 17 - 9 - 1 MDIO 24 - 16 - 8 - 0 - * MDIO Returns status of the mdio_in pin. Use the PHY maintenance register for reading managed frames rather than this bit. * IDLE 0 = The PHY logic is running. 1 = The PHY management logic is idle (i.e., has completed). 644 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.4 Transmit Status Register Register Name: EMAC_TSR Access Type: 31 - 23 - 15 - 7 - Read-write 30 - 22 - 14 - 6 UND 29 - 21 - 13 - 5 COMP 28 - 20 - 12 - 4 BEX 27 - 19 - 11 - 3 TGO 26 - 18 - 10 - 2 RLE 25 - 17 - 9 - 1 COL 24 - 16 - 8 - 0 UBR This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register. * UBR: Used Bit Read Set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit. * COL: Collision Occurred Set by the assertion of collision. Cleared by writing a one to this bit. * RLE: Retry Limit exceeded Cleared by writing a one to this bit. * TGO: Transmit Go If high transmit is active. * BEX: Buffers exhausted mid frame If the buffers run out during transmission of a frame, then transmission stops, FCS shall be bad and tx_er asserted. Cleared by writing a one to this bit. * COMP: Transmit Complete Set when a frame has been transmitted. Cleared by writing a one to this bit. * UND: Transmit Underrun Set when transmit DMA was not able to read data from memory, either because the bus was not granted in time, because a not OK hresp(bus error) was returned or because a used bit was read midway through frame transmission. If this occurs, the transmitter forces bad CRC. Cleared by writing a one to this bit. 645 6384D-ATARM-04-May-09 36.5.5 Receive Buffer Queue Pointer Register Register Name: EMAC_RBQP Access Type: 31 Read-write 30 29 28 ADDR 27 26 25 24 23 22 21 20 ADDR 19 18 17 16 15 14 13 12 ADDR 11 10 9 8 7 6 5 ADDR 4 3 2 1 - 0 - This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original values after either 1024 buffers or when the wrap bit of the entry is set. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. Receive buffer writes also comprise bursts of two words and, as with transmit buffer reads, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1K boundary, in violation of section 3.6 of the AMBA specification. * ADDR: Receive buffer queue pointer address Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. 646 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.6 Transmit Buffer Queue Pointer Register Register Name: EMAC_TBQP Access Type: 31 Read-write 30 29 28 ADDR 27 26 25 24 23 22 21 20 ADDR 19 18 17 16 15 14 13 12 ADDR 11 10 9 8 7 6 5 ADDR 4 3 2 1 - 0 - This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original values after either 1024 buffers or when the wrap bit of the entry is set. This register can only be written when bit 3 in the transmit status register is low. As transmit buffer reads consist of bursts of two words, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1K boundary, in violation of section 3.6 of the AMBA specification. * ADDR: Transmit buffer queue pointer address Written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmitted or about to be transmitted. 647 6384D-ATARM-04-May-09 36.5.7 Receive Status Register Register Name: EMAC_RSR Access Type: 31 - 23 - 15 - 7 - Read-write 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 OVR 25 - 17 - 9 - 1 REC 24 - 16 - 8 - 0 BNA This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register. * BNA: Buffer Not Available An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit. * REC: Frame Received One or more frames have been received and placed in memory. Cleared by writing a one to this bit. * OVR: Receive Overrun The DMA block was unable to store the receive frame to memory, either because the bus was not granted in time or because a not OK hresp(bus error) was returned. The buffer is recovered if this happens. Cleared by writing a one to this bit. 648 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.8 Interrupt Status Register Register Name: EMAC_ISR Access Type: 31 - 23 - 15 - 7 TCOMP Read-write 30 - 22 - 14 - 6 TXERR 29 - 21 - 13 PTZ 5 RLE 28 - 20 - 12 PFR 4 TUND 27 - 19 - 11 HRESP 3 TXUBR 26 - 18 - 10 ROVR 2 RXUBR 25 - 17 - 9 - 1 RCOMP 24 - 16 - 8 - 0 MFD * MFD: Management Frame Done The PHY maintenance register has completed its operation. Cleared on read. * RCOMP: Receive Complete A frame has been stored in memory. Cleared on read. * RXUBR: Receive Used Bit Read Set when a receive buffer descriptor is read with its used bit set. Cleared on read. * TXUBR: Transmit Used Bit Read Set when a transmit buffer descriptor is read with its used bit set. Cleared on read. * TUND: Ethernet Transmit Buffer Underrun The transmit DMA did not fetch frame data in time for it to be transmitted or hresp returned not OK. Also set if a used bit is read mid-frame or when a new transmit queue pointer is written. Cleared on read. * RLE: Retry Limit Exceeded Cleared on read. * TXERR: Transmit Error Transmit buffers exhausted in mid-frame - transmit error. Cleared on read. * TCOMP: Transmit Complete Set when a frame has been transmitted. Cleared on read. * ROVR: Receive Overrun Set when the receive overrun status bit gets set. Cleared on read. * HRESP: Hresp not OK Set when the DMA block sees a bus error. Cleared on read. * PFR: Pause Frame Received Indicates a valid pause has been received. Cleared on a read. * PTZ: Pause Time Zero Set when the pause time register, 0x38 decrements to zero. Cleared on a read. 649 6384D-ATARM-04-May-09 36.5.9 Interrupt Enable Register Register Name: EMAC_IER Access Type: 31 - 23 - 15 - 7 TCOMP Write-only 30 - 22 - 14 - 6 TXERR 29 - 21 - 13 PTZ 5 RLE 28 - 20 - 12 PFR 4 TUND 27 - 19 - 11 HRESP 3 TXUBR 26 - 18 - 10 ROVR 2 RXUBR 25 - 17 - 9 - 1 RCOMP 24 - 16 - 8 - 0 MFD * MFD: Management Frame sent Enable management done interrupt. * RCOMP: Receive Complete Enable receive complete interrupt. * RXUBR: Receive Used Bit Read Enable receive used bit read interrupt. * TXUBR: Transmit Used Bit Read Enable transmit used bit read interrupt. * TUND: Ethernet Transmit Buffer Underrun Enable transmit underrun interrupt. * RLE: Retry Limit Exceeded Enable retry limit exceeded interrupt. * TXERR Enable transmit buffers exhausted in mid-frame interrupt. * TCOMP: Transmit Complete Enable transmit complete interrupt. * ROVR: Receive Overrun Enable receive overrun interrupt. * HRESP: Hresp not OK Enable Hresp not OK interrupt. * PFR: Pause Frame Received Enable pause frame received interrupt. * PTZ: Pause Time Zero Enable pause time zero interrupt. 650 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.10 Interrupt Disable Register Register Name: EMAC_IDR Access Type: 31 - 23 - 15 - 7 TCOMP Write-only 30 - 22 - 14 - 6 TXERR 29 - 21 - 13 PTZ 5 RLE 28 - 20 - 12 PFR 4 TUND 27 - 19 - 11 HRESP 3 TXUBR 26 - 18 - 10 ROVR 2 RXUBR 25 - 17 - 9 - 1 RCOMP 24 - 16 - 8 - 0 MFD * MFD: Management Frame sent Disable management done interrupt. * RCOMP: Receive Complete Disable receive complete interrupt. * RXUBR: Receive Used Bit Read Disable receive used bit read interrupt. * TXUBR: Transmit Used Bit Read Disable transmit used bit read interrupt. * TUND: Ethernet Transmit Buffer Underrun Disable transmit underrun interrupt. * RLE: Retry Limit Exceeded Disable retry limit exceeded interrupt. * TXERR Disable transmit buffers exhausted in mid-frame interrupt. * TCOMP: Transmit Complete Disable transmit complete interrupt. * ROVR: Receive Overrun Disable receive overrun interrupt. * HRESP: Hresp not OK Disable Hresp not OK interrupt. * PFR: Pause Frame Received Disable pause frame received interrupt. * PTZ: Pause Time Zero Disable pause time zero interrupt. 651 6384D-ATARM-04-May-09 36.5.11 Interrupt Mask Register Register Name: EMAC_IMR Access Type: 31 - 23 - 15 - 7 TCOMP Read-only 30 - 22 - 14 - 6 TXERR 29 - 21 - 13 PTZ 5 RLE 28 - 20 - 12 PFR 4 TUND 27 - 19 - 11 HRESP 3 TXUBR 26 - 18 - 10 ROVR 2 RXUBR 25 - 17 - 9 - 1 RCOMP 24 - 16 - 8 - 0 MFD * MFD: Management Frame sent Management done interrupt masked. * RCOMP: Receive Complete Receive complete interrupt masked. * RXUBR: Receive Used Bit Read Receive used bit read interrupt masked. * TXUBR: Transmit Used Bit Read Transmit used bit read interrupt masked. * TUND: Ethernet Transmit Buffer Underrun Transmit underrun interrupt masked. * RLE: Retry Limit Exceeded Retry limit exceeded interrupt masked. * TXERR Transmit buffers exhausted in mid-frame interrupt masked. * TCOMP: Transmit Complete Transmit complete interrupt masked. * ROVR: Receive Overrun Receive overrun interrupt masked. * HRESP: Hresp not OK Hresp not OK interrupt masked. * PFR: Pause Frame Received Pause frame received interrupt masked. * PTZ: Pause Time Zero Pause time zero interrupt masked. 652 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.12 PHY Maintenance Register Register Name: EMAC_MAN Access Type: 31 SOF 23 PHYA 15 22 21 Read-write 30 29 RW 20 REGA 12 DATA 19 18 28 27 26 PHYA 17 CODE 11 10 9 8 16 25 24 14 13 7 6 5 4 DATA 3 2 1 0 * DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. * CODE: Must be written to 10. Reads as written. * REGA: Register Address Specifies the register in the PHY to access. * PHYA: PHY Address * RW: Read-write 10 is read; 01 is write. Any other value is an invalid PHY management frame * SOF: Start of frame Must be written 01 for a valid frame. 653 6384D-ATARM-04-May-09 36.5.13 Pause Time Register Register Name: EMAC_PTR Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 PTIME 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 PTIME 3 2 1 0 * PTIME: Pause Time Stores the current value of the pause time register which is decremented every 512 bit times. 654 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.14 Hash Register Bottom Register Name: EMAC_HRB Access Type: 31 Read-write 30 29 28 ADDR 27 26 25 24 23 22 21 20 ADDR 19 18 17 16 15 14 13 12 ADDR 11 10 9 8 7 6 5 4 ADDR 3 2 1 0 * ADDR: Bits 31:0 of the hash address register. See "Hash Addressing" on page 632. 36.5.15 Hash Register Top Register Name: EMAC_HRT Access Type: 31 Read-write 30 29 28 ADDR 27 26 25 24 23 22 21 20 ADDR 19 18 17 16 15 14 13 12 ADDR 11 10 9 8 7 6 5 4 ADDR 3 2 1 0 * ADDR: Bits 63:32 of the hash address register. See "Hash Addressing" on page 632. 655 6384D-ATARM-04-May-09 36.5.16 Specific Address 1 Bottom Register Register Name: EMAC_SA1B Access Type: 31 Read-write 30 29 28 ADDR 27 26 25 24 23 22 21 20 ADDR 19 18 17 16 15 14 13 12 ADDR 11 10 9 8 7 6 5 4 ADDR 3 2 1 0 * ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 36.5.17 Specific Address 1 Top Register Register Name: EMAC_SA1T Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 ADDR 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 ADDR 3 2 1 0 * ADDR The most significant bits of the destination address, that is bits 47 to 32. 656 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.18 Specific Address 2 Bottom Register Register Name: EMAC_SA2B Access Type: 31 Read-write 30 29 28 ADDR 27 26 25 24 23 22 21 20 ADDR 19 18 17 16 15 14 13 12 ADDR 11 10 9 8 7 6 5 4 ADDR 3 2 1 0 * ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 36.5.19 Specific Address 2 Top Register Register Name: EMAC_SA2T Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 ADDR 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 ADDR 3 2 1 0 * ADDR The most significant bits of the destination address, that is bits 47 to 32. 657 6384D-ATARM-04-May-09 36.5.20 Specific Address 3 Bottom Register Register Name: EMAC_SA3B Access Type: 31 Read-write 30 29 28 ADDR 27 26 25 24 23 22 21 20 ADDR 19 18 17 16 15 14 13 12 ADDR 11 10 9 8 7 6 5 4 ADDR 3 2 1 0 * ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 36.5.21 Specific Address 3 Top Register Register Name: EMAC_SA3T Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 ADDR 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 ADDR 3 2 1 0 * ADDR The most significant bits of the destination address, that is bits 47 to 32. 658 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.22 Specific Address 4 Bottom Register Register Name: EMAC_SA4B Access Type: 31 Read-write 30 29 28 ADDR 27 26 25 24 23 22 21 20 ADDR 19 18 17 16 15 14 13 12 ADDR 11 10 9 8 7 6 5 4 ADDR 3 2 1 0 * ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 36.5.23 Specific Address 4 Top Register Register Name: EMAC_SA4T Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 ADDR 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 ADDR 3 2 1 0 * ADDR The most significant bits of the destination address, that is bits 47 to 32. 659 6384D-ATARM-04-May-09 36.5.24 Type ID Checking Register Register Name: EMAC_TID Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 TID 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 TID 3 2 1 0 * TID: Type ID checking For use in comparisons with received frames TypeID/Length field. 36.5.25 User Input/Output Register Register Name: EMAC_USRIO Access Type: 31 - 23 - 15 - 7 - Read-write 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 CLKEN 24 - 16 - 8 - 0 RMII * RMII When set, this bit enables the RMII operation mode. When reset, it selects the MII mode. * CLKEN When set, this bit enables the transceiver input clock. Setting this bit to 0 reduces power consumption when the treasurer is not used. 660 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.26 EMAC Statistic Registers These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the following registers. 36.5.26.1 Pause Frames Received Register Register Name: EMAC_PFR Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 FROK 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 FROK 3 2 1 0 * FROK: Pause Frames received OK A 16-bit register counting the number of good pause frames received. A good frame has a length of 64 to 1518 (1536 if bit 8 set in network configuration register) and has no FCS, alignment or receive symbol errors. 36.5.26.2 Frames Transmitted OK Register Register Name: EMAC_FTO Access Type: 31 - 23 Read-write 30 - 22 29 - 21 28 - 20 FTOK 27 - 19 26 - 18 25 - 17 24 - 16 15 14 13 12 FTOK 11 10 9 8 7 6 5 4 FTOK 3 2 1 0 * FTOK: Frames Transmitted OK A 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries. 661 6384D-ATARM-04-May-09 36.5.26.3 Single Collision Frames Register Register Name: EMAC_SCF Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 SCF 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 SCF 3 2 1 0 * SCF: Single Collision Frames A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. 36.5.26.4 Multicollision Frames Register Register Name: EMAC_MCF Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 MCF 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 MCF 3 2 1 0 * MCF: Multicollision Frames A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no underrun and not too many retries. 662 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.26.5 Frames Received OK Register Register Name: EMAC_FRO Access Type: 31 - 23 Read-write 30 - 22 29 - 21 28 - 20 FROK 27 - 19 26 - 18 25 - 17 24 - 16 15 14 13 12 FROK 11 10 9 8 7 6 5 4 FROK 3 2 1 0 * FROK: Frames Received OK A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory. A good frame is of length 64 to 1518 bytes (1536 if bit 8 set in network configuration register) and has no FCS, alignment or receive symbol errors. 36.5.26.6 Frames Check Sequence Errors Register Register Name: EMAC_FCSE Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FCSE 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * FCSE: Frame Check Sequence Errors An 8-bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes. 663 6384D-ATARM-04-May-09 36.5.26.7 Alignment Errors Register Register Name: EMAC_ALE Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 ALE 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * ALE: Alignment Errors An 8-bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes. 36.5.26.8 Deferred Transmission Frames Register Register Name: EMAC_DTF Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 DTF 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 DTF 3 2 1 0 * DTF: Deferred Transmission Frames A 16-bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit underrun. 664 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.26.9 Late Collisions Register Register Name: EMAC_LCOL Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 LCOL 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * LCOL: Late Collisions An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision. 36.5.26.10 Excessive Collisions Register Register Name: EMAC_ECOL Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 EXCOL 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * EXCOL: Excessive Collisions An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions. 665 6384D-ATARM-04-May-09 36.5.26.11 Transmit Underrun Errors Register Register Name: EMAC_TUND Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TUND 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * TUND: Transmit Underruns An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented. 36.5.26.12 Carrier Sense Errors Register Register Name: EMAC_CSE Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 CSE 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * CSE: Carrier Sense Errors An 8-bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no underrun). Only incremented in half-duplex mode. The only effect of a carrier sense error is to increment this register. The behavior of the other statistics registers is unaffected by the detection of a carrier sense error. 666 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.26.13 Receive Resource Errors Register Register Name: EMAC_RRE Access Type: 31 - 23 - 15 Read-write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RRE 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 RRE 3 2 1 0 * RRE: Receive Resource Errors A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 36.5.26.14 Receive Overrun Errors Register Register Name: EMAC_ROV Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 ROVR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * ROVR: Receive Overrun An 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun. 667 6384D-ATARM-04-May-09 36.5.26.15 Receive Symbol Errors Register Register Name: EMAC_RSE Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RSE 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * RSE: Receive Symbol Errors An 8-bit register counting the number of frames that had rx_er asserted during reception. Receive symbol errors are also counted as an FCS or alignment error if the frame is between 64 and 1518 bytes in length (1536 if bit 8 is set in the network configuration register). If the frame is larger, it is recorded as a jabber error. 36.5.26.16 Excessive Length Errors Register Register Name: EMAC_ELE Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 EXL 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * EXL: Excessive Length Errors An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length but do not have either a CRC error, an alignment error nor a receive symbol error. 668 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 36.5.26.17 Receive Jabbers Register Register Name: EMAC_RJA Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RJB 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * RJB: Receive Jabbers An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error. 36.5.26.18 Undersize Frames Register Register Name: EMAC_USF Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 USF 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * USF: Undersize frames An 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error. 669 6384D-ATARM-04-May-09 36.5.26.19 SQE Test Errors Register Register Name: EMAC_STE Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 SQER 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * SQER: SQE test errors An 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. 36.5.26.20 Received Length Field Mismatch Register Register Name: EMAC_RLE Access Type: 31 - 23 - 15 - 7 Read-write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RLFM 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * RLFM: Receive Length Field Mismatch An 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field. Checking is enabled through bit 16 of the network configuration register. Frames containing a type ID in bytes 13 and 14 (i.e., length/type ID 0x0600) are not counted as length field errors, neither are excessive length frames. 670 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 37. USB Device Port (UDP) 37.1 Overview The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral. This feature is mandatory for isochronous endpoints. Thus the device maintains the maximum bandwidth (1M bytes/s) by working with endpoints with two banks of DPR. Table 37-1. USB Endpoint Description Mnemonic EP0 EP1 EP2 EP3 EP4 EP5 Dual-Bank(1) No Yes Yes No Yes Yes Max. Endpoint Size 64 64 64 64 512 512 Endpoint Type Control/Bulk/Interrupt Bulk/Iso/Interrupt Bulk/Iso/Interrupt Control/Bulk/Interrupt Bulk/Iso/Interrupt Bulk/Iso/Interrupt Endpoint Number 0 1 2 3 4 5 Note: 1. The Dual-Bank function provides two banks for an endpoint. This feature is used for ping-pong mode. Suspend and resume are automatically detected by the USB device, which notifies the processor by raising an interrupt. Depending on the product, an external signal can be used to send a wake up to the USB host controller. 671 6384D-ATARM-04-May-09 37.2 Block Diagram Figure 37-1. Block Diagram Atmel Bridge APB to MCU Bus USB Device txoen MCK UDPCK U s e r I n t e r f a c e W r a p p e r Dual Port RAM FIFO W r a p p e r eopn Serial Interface Engine 12 MHz txd rxdm rxd rxdp Embedded USB Transceiver DP DM SIE udp_int Suspend/Resume Logic Master Clock Domain Recovered 12 MHz Domain external_resume Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers. The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48 MHz clock (UDPCK) used by the 12 MHz domain. A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE). The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode. The host is then notified that the device asks for a resume. This optional feature must be also negotiated with the host during the enumeration. 37.3 Product Dependencies For further details on the USB Device hardware implementation, see the specific Product Properties document. The USB physical transceiver is integrated into the product. The bidirectional differential signals DP and DM are available from the product boundary. One I/O line may be used by the application to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off. In this case, the pullup on DP must be disabled in order to prevent feeding current to the host. The application should disconnect the transceiver, then remove the pullup. 37.3.1 I/O Lines DP and DM are not controlled by any PIO controllers. The embedded USB physical transceiver is controlled by the USB device peripheral. 672 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary To reserve an I/O line to check VBUS, the programmer must first program the PIO controller to assign this I/O in input PIO mode. 37.3.2 Power Management The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL with an accuracy of 0.25%. Thus, the USB device receives two clocks from the Power Management Controller (PMC): the master clock, MCK, used to drive the peripheral user interface, and the UDPCK, used to interface with the bus USB signals (recovered 12 MHz domain). WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXCV register. 37.3.3 Interrupt The USB device interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the USB device interrupt requires programming the AIC before configuring the UDP. 673 6384D-ATARM-04-May-09 37.4 Typical Connection Figure 37-2. Board Schematic to Interface Device Peripheral PIO 5V Bus Monitoring 27 K 47 K REXT DDM DDP REXT 2 1 3 Type B 4 Connector 37.4.1 USB Device Transceiver The USB device transceiver is embedded in the product. A few discrete components are required as follows: * the application detects all device states as defined in chapter 9 of the USB specification; - VBUS monitoring * to reduce power consumption the host is disconnected * for line termination. 37.4.2 VBUS Monitoring VBUS monitoring is required to detect host connection. VBUS monitoring is done using a standard PIO with internal pullup disabled. When the host is switched off, it should be considered as a disconnect, the pullup must be disabled in order to prevent powering the host through the pullup resistor. When the host is disconnected and the transceiver is enabled, then DDP and DDM are floating. This may lead to over consumption. A solution is to enable the integrated pulldown by disabling the transceiver (TXVDIS = 1) and then remove the pullup (PUON = 0). A termination serial resistor must be connected to DP and DM. The resistor value is defined in the electrical specification of the product (REXT). 674 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 37.5 37.5.1 Functional Description USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of communication flows. Figure 37-3. Example of USB V2.0 Full-speed Communication Control USB Host V2.0 Software Client 1 Software Client 2 Data Flow: Control Transfer Data Flow: Isochronous In Transfer Data Flow: Isochronous Out Transfer EP0 USB Device 2.0 EP1 Block 1 EP2 Data Flow: Control Transfer Data Flow: Bulk In Transfer Data Flow: Bulk Out Transfer EP0 USB Device 2.0 EP4 Block 2 EP5 USB Device endpoint configuration requires that in the first instance Control Transfer must be EP0. The Control Transfer endpoint EP0 is always used when a USB device is first configured (USB v. 2.0 specifications). 37.5.1.1 USB V2.0 Full-speed Transfer Types A communication flow is carried over one of four transfer types defined by the USB device. USB Communication Flow Direction Bidirectional Unidirectional Unidirectional Unidirectional Bandwidth Not guaranteed Guaranteed Not guaranteed Not guaranteed Supported Endpoint Size 8, 16, 32, 64 512 64 8, 16, 32, 64 Error Detection Yes Yes Yes Yes Retrying Automatic No Yes Yes Table 37-2. Transfer Control Isochronous Interrupt Bulk 37.5.1.2 USB Bus Transactions Each transfer results in one or more transactions over the USB bus. There are three kinds of transactions flowing across the bus in packets: 675 6384D-ATARM-04-May-09 1. Setup Transaction 2. Data IN Transaction 3. Data OUT Transaction 37.5.1.3 USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 37-3. USB Transfer Events * Setup transaction > Data IN transactions > Status OUT transaction Control Transfers(1) (3) * Setup transaction > Data OUT transactions > Status IN transaction * Setup transaction > Status IN transaction * Data IN transaction > Data IN transaction * Data OUT transaction > Data OUT transaction * Data IN transaction > Data IN transaction * Data OUT transaction > Data OUT transaction * Data IN transaction > Data IN transaction * Data OUT transaction > Data OUT transaction Interrupt IN Transfer (device toward host) Interrupt OUT Transfer (host toward device) Isochronous IN Transfer(2) (device toward host) Isochronous OUT Transfer(2) (host toward device) Bulk IN Transfer (device toward host) Bulk OUT Transfer (host toward device) Notes: 1. Control transfer must use endpoints with no ping-pong attributes. 2. Isochronous transfers must use endpoints with ping-pong attributes. 3. Control transfers can be aborted using a stall handshake. A status transaction is a special type of host-to-device transaction used only in a control transfer. The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction. 676 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 37-4. Control Read and Write Sequences Setup Stage Data Stage Status Stage Control Read Setup TX Data OUT TX Data OUT TX Status IN TX Setup Stage Data Stage Status Stage Control Write Setup TX Data IN TX Data IN TX Status OUT TX Setup Stage Status Stage No Data Control Notes: Setup TX Status IN TX 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol layer. 2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data). 37.5.2 37.5.2.1 Handling Transactions with USB V2.0 Device Peripheral Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer. When a setup transfer is received by the USB endpoint: * The USB device automatically acknowledges the setup packet * RXSETUP is set in the UDP_CSRx register * An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect the RXSETUP polling the UDP_CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO. 677 6384D-ATARM-04-May-09 Figure 37-5. Setup Transaction Followed by a Data OUT Transaction Setup Received Setup Handled by Firmware Data Out Received USB Bus Packets Setup PID Data Setup ACK PID Data OUT PID Data OUT NAK PID Data OUT PID Data OUT ACK PID RXSETUP Flag Interrupt Pending Set by USB Device Cleared by Firmware Set by USB Device Peripheral RX_Data_BKO (UDP_CSRx) FIFO (DPR) Content XX Data Setup XX Data OUT 37.5.2.2 Data IN Transaction Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong attributes. Using Endpoints Without Ping-pong Attributes To perform a Data IN transaction using a non ping-pong endpoint: 1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint's UDP_CSRx register (TXPKTRDY must be cleared). 2. The application writes the first packet of data to be sent in the endpoint's FIFO, writing zero or more byte values in the endpoint's UDP_FDRx register, 3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint's UDP_CSRx register. 4. The application is notified that the endpoint's FIFO has been released by the USB device when TXCOMP in the endpoint's UDP_CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. 5. The microcontroller writes the second packet of data to be sent in the endpoint's FIFO, writing zero or more byte values in the endpoint's UDP_FDRx register, 6. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint's UDP_CSRx register. 7. The application clears the TXCOMP in the endpoint's UDP_CSRx. After the last packet has been sent, the application must clear TXCOMP once this has been set. TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set. Warning: TX_COMP must be cleared after TX_PKTRDY has been set. Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN protocol layer. 37.5.2.3 678 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 37-6. Data IN Transfer for Non Ping-pong Endpoint Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus USB Bus Packets Data IN PID Data IN 1 ACK PID Data IN PID NAK PID Data IN PID Data IN 2 ACK PID TXPKTRDY Flag (UDP_CSRx) Set by the firmware Cleared by Hw Set by the firmware Cleared by Hw Interrupt Pending Payload in FIFO Cleared by Firmware DPR access by the firmware FIFO (DPR) Content Data IN 1 Load In Progress DPR access by the hardware Data IN 2 Cleared by Firmware Interrupt Pending TXCOMP Flag (UDP_CSRx) 37.5.2.4 Using Endpoints With Ping-pong Attribute The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows handling the maximum bandwidth defined in the USB specification during bulk transfer. To be able to guarantee a constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 37-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints Microcontroller Write Bank 0 Endpoint 1 USB Device Read USB Bus 1st Data Payload Read and Write at the Same Time 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Bank 0 Endpoint 1 Data IN Packet 1st Data Payload Data IN Packet 2nd Data Payload Bank 0 Endpoint 1 Data IN Packet 3rd Data Payload When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 679 6384D-ATARM-04-May-09 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint's UDP_CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint's UDP_FDRx register. 3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint's UDP_CSRx register. 4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint's UDP_FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint's UDP_CSRx register is set. An interrupt is pending while TXCOMP is being set. 6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent, raising TXPKTRDY in the endpoint's UDP_CSRx register. 7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent. Figure 37-8. Data IN Transfer for Ping-pong Endpoint Microcontroller Load Data IN Bank 0 Microcontroller Load Data IN Bank 1 USB Device Send Bank 0 Microcontroller Load Data IN Bank 0 USB Device Send Bank 1 USB Bus Packets Data IN PID Data IN ACK PID Data IN PID Data IN ACK PID TXPKTRDY Flag (UDP_MCSRx) Set by Firmware, Data Payload Written in FIFO Bank 0 TXCOMP Flag (UDP_CSRx) Cleared by USB Device, Data Payload Fully Transmitted Set by USB Device Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending Set by USB Device Interrupt Cleared by Firmware FIFO (DPR) Written by Microcontroller Bank 0 Read by USB Device Written by Microcontroller FIFO (DPR) Bank 1 Written by Microcontroller Read by USB Device Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long, some Data IN packets may be NACKed, reducing the bandwidth. Warning: TX_COMP must be cleared after TX_PKTRDY has been set. 680 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 37.5.2.5 Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint's UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint's UDP_CSRx register. 5. The microcontroller carries out data received from the endpoint's memory to its memory. Data received is available by reading the endpoint's UDP_FDRx register. 6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint's UDP_CSRx register. 7. A new Data OUT packet can be accepted by the USB device. Figure 37-9. Data OUT Transfer for Non Ping-pong Endpoints Host Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Host Resends the Next Data Payload 37.5.2.6 USB Bus Packets Data OUT PID Data OUT 1 ACK PID Data OUT2 PID Data OUT2 NAK PID Data OUT PID Data OUT2 ACK PID RX_DATA_BK0 (UDP_CSRx) Interrupt Pending Set by USB Device Cleared by Firmware, Data Payload Written in FIFO Data OUT 2 Written by USB Device FIFO (DPR) Content Data OUT 1 Written by USB Device Data OUT 1 Microcontroller Read An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO. 37.5.2.7 Using Endpoints With Ping-pong Attributes During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data pay681 6384D-ATARM-04-May-09 load sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 37-10. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints Microcontroller Write USB Device Read Bank 0 Endpoint 1 Data IN Packet 1st Data Payload USB Bus Write and Read at the Same Time 1st Data Payload Bank 0 Endpoint 1 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Data IN Packet nd Data Payload 2 Bank 0 Endpoint 1 Data IN Packet 3rd Data Payload When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint's FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint's UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint's UDP_CSRx register. 6. The microcontroller transfers out data received from the endpoint's memory to the microcontroller's memory. Data received is made available by reading the endpoint's UDP_FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint's UDP_CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint's UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set. 10. The microcontroller transfers out data received from the endpoint's memory to the microcontroller's memory. Data received is available by reading the endpoint's UDP_FDRx register. 682 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint's UDP_CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0. Figure 37-11. Data OUT Transfer for Ping-pong Endpoint Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0, Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1, Host Sends Third Data Payload USB Bus Packets Data OUT PID Data OUT 1 ACK PID Data OUT PID Data OUT 2 ACK PID Data OUT PID Data OUT 3 A P RX_DATA_BK0 Flag (UDP_CSRx) Interrupt Pending Set by USB Device, Data Payload Written in FIFO Endpoint Bank 0 Cleared by Firmware RX_DATA_BK1 Flag (UDP_CSRx) Set by USB Device, Data Payload Written in FIFO Endpoint Bank 1 Cleared by Firmware Interrupt Pending FIFO (DPR) Bank 0 Data OUT1 Write by USB Device Data OUT 1 Read By Microcontroller Data OUT 3 Write In Progress FIFO (DPR) Bank 1 Data OUT 2 Write by USB Device Data OUT 2 Read By Microcontroller Note: An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set. Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set. 37.5.2.8 Stall Handshake A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.) * A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.) * To abort the current request, a protocol stall is used, but uniquely with control transfer. The following procedure generates a stall packet: 1. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint's register. 2. The host receives the stall packet. 683 6384D-ATARM-04-May-09 3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt. When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set. Figure 37-12. Stall Handshake (Data IN Transfer) USB Bus Packets Data IN PID Stall PID Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device Figure 37-13. Stall Handshake (Data OUT Transfer) USB Bus Packets Data OUT PID Data OUT Stall PID FORCESTALL Set by Firmware Interrupt Pending STALLSENT Set by USB Device Cleared by Firmware 684 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 37.5.2.9 Transmit Data Cancellation Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel transmission data held in these banks is described below. To see the organization of dual-bank availability refer to Table 37-1 "USB Endpoint Description". 37.5.2.10 Endpoints Without Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set. * TXPKTRDY is not set: - Reset the endpoint to clear the FIFO (pointers). (See, Section 37.6.9 "UDP Reset Endpoint Register".) * TXPKTRDY has already been set: - Clear TXPKTRDY so that no packet is ready to be sent - Reset the endpoint to clear the FIFO (pointers). (See, Section 37.6.9 "UDP Reset Endpoint Register".) 37.5.2.11 Endpoints With Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set. * TXPKTRDY is not set: - Reset the endpoint to clear the FIFO (pointers). (See, Section 37.6.9 "UDP Reset Endpoint Register".) * TXPKTRDY has already been set: - Clear TXPKTRDY and read it back until actually read at 0. - Set TXPKTRDY and read it back until actually read at 1. - Clear TXPKTRDY so that no packet is ready to be sent. - Reset the endpoint to clear the FIFO (pointers). (See, Section 37.6.9 "UDP Reset Endpoint Register".) 685 6384D-ATARM-04-May-09 37.5.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 37-14. USB Device State Diagram Attached Hub Reset or Deconfigured Hub Configured Bus Inactive Powered Bus Activity Power Interruption Suspended Reset Bus Inactive Default Reset Address Assigned Bus Inactive Bus Activity Suspended Address Bus Activity Device Deconfigured Device Configured Bus Inactive Suspended Configured Bus Activity Suspended Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 A on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake up request to the host, e.g., waking up a PC by moving a USB mouse. The wake up feature is not mandatory for all devices and must be negotiated with the host. 686 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 37.5.3.1 Not Powered State Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the device is not connected to a host, device power consumption can be reduced by disabling MCK for the UDP, disabling UDPCK and disabling the transceiver. DDP and DDM lines are pulled down by 330 K resistors. Entering Attached State When no device is connected, the USB DP and DM signals are tied to GND by 15 K pull-down resistors integrated in the hub downstream ports. When a device is attached to a hub downstream port, the device connects a 1.5 K pull-up resistor on DP. The USB bus line goes into IDLE state, DP is pulled up by the device 1.5 K resistor to 3.3V and DM is pulled down by the 15 K resistor of the host. To enable integrated pullup, the PUON bit in the UDP_TXVC register must be set. Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP. This is done in the Power Management Controller. After pullup connection, the device enters the powered state. In this state, the UDPCK and MCK must be enabled in the Power Management Controller. The transceiver can remain disabled. 37.5.3.3 From Powered State to Default State After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmaskable flag ENDBUSRES is set in the register UDP_ISR and an interrupt is triggered. Once the ENDBUSRES interrupt has been triggered, the device enters Default State. In this state, the UDP software must: * Enable the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer. * Configure the interrupt mask register which has been reset by the USB reset detection * Enable the transceiver clearing the TXVDIS flag in the UDP_TXVC register. In this state UDPCK and MCK must be enabled. Warning: Each time an ENDBUSRES interrupt is triggered, the Interrupt Mask Register and UDP_CSR registers have been reset. 37.5.3.4 From Default State to Address State After a set address standard device request, the USB host peripheral enters the address state. Warning: Before the device enters in address state, it must achieve the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared. To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STAT register, sets its new address, and sets the FEN bit in the UDP_FADDR register. 37.5.3.5 From Address State to Configured State Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register. 37.5.3.2 687 6384D-ATARM-04-May-09 37.5.3.6 Entering in Suspend State When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register.This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. In this state bus powered devices must drain less than 500uA from the 5V VBUS. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The USB device peripheral clocks can be switched off. Resume event is asynchronously detected. MCK and UDPCK can be switched off in the Power Management controller and the USB transceiver can be disabled by setting the TXVDIS field in the UDP_TXVC register. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations after writing to the UDP_TXVC and acknowledging the RXSUSP. 37.5.3.7 Receiving a Host Resume In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pullup shall not be removed). Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake up the core, enable PLL and main oscillators and configure clocks. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. MCK for the UDP must be enabled before clearing the WAKEUP bit in the UDP_ICR register and clearing TXVDIS in the UDP_TXVC register. 37.5.3.8 Sending a Device Remote Wakeup In Suspend state it is possible to wake up the host sending an external resume. * The device must wait at least 5 ms after being entered in suspend before sending an external resume. * The device has 10 ms from the moment it starts to drain current and it forces a K state to resume the host. * The device must force a K state from 1 to 15 ms to resume the host To force a K state to the bus (DM at 3.3V and DP tied to GND), it is possible to use a transistor to connect a pullup on DM. The K state is obtained by disabling the pullup on DP and enabling the pullup on DM. This should be under the control of the application. 688 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 37-15. Board Schematic to Drive a K State 3V3 PIO 0: Force Wake UP (K State) 1: Normal Mode 1.5 K DM 689 6384D-ATARM-04-May-09 37.6 USB Device (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers, including the UDP_TXVC register. Table 37-4. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C Register Mapping Register Frame Number Register Global State Register Function Address Register Reserved Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Reserved Reset Endpoint Register Reserved Endpoint Control and Status Register Endpoint FIFO Data Register Reserved Transceiver Control Register Reserved Name UDP_FRM_NUM UDP_GLB_STAT UDP_FADDR - UDP_IER UDP_IDR UDP_IMR UDP_ISR UDP_ICR - UDP_RST_EP - UDP_CSR UDP_FDR - UDP_TXVC - (2) Access Read-only Read-write Read-write - Write-only Write-only Read-only Read-only Write-only - Read-write - Read-write Read-write - Read-write - Reset 0x0000_0000 0x0000_0000 0x0000_0100 - 0x0000_1200 -(1) - 0x0000_0000 - 0x0000_0000 0x0000_0000 - 0x0000_0100 - 0x030 + 0x4 * ( ept_num - 1 ) 0x050 + 0x4 * ( ept_num - 1 ) 0x070 0x074 0x078 - 0xFC Notes: 1. Reset values are not defined for UDP_ISR. 2. See Warning above the "Register Mapping" on this page. 690 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 37.6.1 UDP Frame Number Register Register Name:UDP_FRM_NUM Access Type: Read-only 31 --23 - 15 - 7 30 --22 - 14 - 6 29 --21 - 13 - 5 28 --20 - 12 - 4 FRM_NUM 27 --19 - 11 - 3 26 --18 - 10 25 --17 FRM_OK 9 FRM_NUM 1 24 --16 FRM_ERR 8 2 0 * FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet). * FRM_ERR: Frame Error This bit is set at SOF_EOP when the SOF packet is received containing an error. This bit is reset upon receipt of SOF_PID. * FRM_OK: Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error. This bit is reset upon receipt of SOF_PID (Packet Identification). In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP. Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L. 691 6384D-ATARM-04-May-09 37.6.2 UDP Global State Register Register Name:UDP_GLB_STAT Access Type: Read-write 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 RSMINPR 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 CONFG 24 - 16 - 8 - 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. * FADDEN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = No effect, only a reset can bring back a device to the default state. 1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. * CONFG: Configured Read: 0 = Device is not in configured state. 1 = Device is in configured state. Write: 0 = Sets device in a non configured state 1 = Sets device in configured state. The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. * RSMINPR: Resume Interrupt Request Read: 0 = No effect. 1 = The pin "send_resume" is set to one. A Send Resume request has been detected and the device can send a Remote Wake Up. 692 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 37.6.3 UDP Function Address Register Register Name:UDP_FADDR Access Type: Read-write 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 27 - 19 - 11 - 3 FADD 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 FEN 0 * FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. After power up or reset, the function address value is set to 0. * FEN: Function Enable Read: 0 = Function endpoint disabled. 1 = Function endpoint enabled. Write: 0 = Disables function endpoint. 1 = Default value. The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host. 693 6384D-ATARM-04-May-09 37.6.4 UDP Interrupt Enable Register Register Name:UDP_IER Access Type: Write-only 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 WAKEUP 5 EP5INT 28 - 20 - 12 - 4 EP4INT 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 EXTRSM 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT * EP0INT: Enable Endpoint 0 Interrupt * EP1INT: Enable Endpoint 1 Interrupt * EP2INT: Enable Endpoint 2Interrupt * EP3INT: Enable Endpoint 3 Interrupt * EP4INT: Enable Endpoint 4 Interrupt * EP5INT: Enable Endpoint 5 Interrupt 0 = No effect. 1 = Enables corresponding Endpoint Interrupt. * RXSUSP: Enable UDP Suspend Interrupt 0 = No effect. 1 = Enables UDP Suspend Interrupt. * RXRSM: Enable UDP Resume Interrupt 0 = No effect. 1 = Enables UDP Resume Interrupt. * EXTRSM: Enable External Resume Interrupt 0 = No effect. 1 = Enables External Resume Interrupt. * SOFINT: Enable Start Of Frame Interrupt 0 = No effect. 1 = Enables Start Of Frame Interrupt. * WAKEUP: Enable UDP bus Wakeup Interrupt 0 = No effect. 1 = Enables USB bus Interrupt. 694 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 37.6.5 UDP Interrupt Disable Register Register Name:UDP_IDR Access Type: Write-only 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 WAKEUP 5 EP5INT 28 - 20 - 12 - 4 EP4INT 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 EXTRSM 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT * EP0INT: Disable Endpoint 0 Interrupt * EP1INT: Disable Endpoint 1 Interrupt * EP2INT: Disable Endpoint 2 Interrupt * EP3INT: Disable Endpoint 3 Interrupt * EP4INT: Disable Endpoint 4 Interrupt * EP5INT: Disable Endpoint 5 Interrupt 0 = No effect. 1 = Disables corresponding Endpoint Interrupt. * RXSUSP: Disable UDP Suspend Interrupt 0 = No effect. 1 = Disables UDP Suspend Interrupt. * RXRSM: Disable UDP Resume Interrupt 0 = No effect. 1 = Disables UDP Resume Interrupt. * EXTRSM: Disable External Resume Interrupt 0 = No effect. 1 = Disables External Resume Interrupt. * SOFINT: Disable Start Of Frame Interrupt 0 = No effect. 1 = Disables Start Of Frame Interrupt * WAKEUP: Disable USB Bus Interrupt 0 = No effect. 1 = Disables USB Bus Wakeup Interrupt. 695 6384D-ATARM-04-May-09 37.6.6 UDP Interrupt Mask Register Register Name:UDP_IMR Access Type: Read-only 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 WAKEUP 5 EP5INT 28 - 20 - 12 BIT12 4 EP4INT 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 EXTRSM 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT * EP0INT: Mask Endpoint 0 Interrupt * EP1INT: Mask Endpoint 1 Interrupt * EP2INT: Mask Endpoint 2 Interrupt * EP3INT: Mask Endpoint 3 Interrupt * EP4INT: Mask Endpoint 4 Interrupt * EP5INT: Mask Endpoint 5 Interrupt 0 = Corresponding Endpoint Interrupt is disabled. 1 = Corresponding Endpoint Interrupt is enabled. * RXSUSP: Mask UDP Suspend Interrupt 0 = UDP Suspend Interrupt is disabled. 1 = UDP Suspend Interrupt is enabled. * RXRSM: Mask UDP Resume Interrupt. 0 = UDP Resume Interrupt is disabled. 1 = UDP Resume Interrupt is enabled. * EXTRSM: Mask External Resume Interrupt 0 = UDP External Resume Interrupt is disabled. 1 = UDP External Resume Interrupt is enabled. * SOFINT: Mask Start Of Frame Interrupt 0 = Start of Frame Interrupt is disabled. 1 = Start of Frame Interrupt is enabled. 696 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * BIT12: UDP_IMR Bit 12 Bit 12 of UDP_IMR cannot be masked and is always read at 1. * WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wakeup Interrupt is disabled. 1 = USB Bus Wakeup Interrupt is enabled. Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_IMR is enabled. 697 6384D-ATARM-04-May-09 37.6.7 UDP Interrupt Status Register Register Name:UDP_ISR Access Type: Read-only 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 WAKEUP 5 EP5INT 28 - 20 - 12 ENDBUSRES 4 EP4INT 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 EXTRSM 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT * EP0INT: Endpoint 0 Interrupt Status * EP1INT: Endpoint 1 Interrupt Status * EP2INT: Endpoint 2 Interrupt Status * EP3INT: Endpoint 3 Interrupt Status * EP4INT: Endpoint 4 Interrupt Status * EP5INT: Endpoint 5 Interrupt Status 0 = No Endpoint0 Interrupt pending. 1 = Endpoint0 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_CSR0: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_CSR0 bit. * RXSUSP: UDP Suspend Interrupt Status 0 = No UDP Suspend Interrupt pending. 1 = UDP Suspend Interrupt has been raised. The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode. * RXRSM: UDP Resume Interrupt Status 0 = No UDP Resume Interrupt pending. 1 =UDP Resume Interrupt has been raised. 698 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR register. * EXTRSM: UDP External Resume Interrupt Status 0 = No UDP External Resume Interrupt pending. 1 = UDP External Resume Interrupt has been raised. * SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. * ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the endpoint 0. The host starts the enumeration, then performs the configuration. * WAKEUP: UDP Resume Interrupt Status 0 = No Wakeup Interrupt pending. 1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear. After reset the state of this bit is undefined, the application must clear this bit by setting the WAKEUP flag in the UDP_ICR register. 699 6384D-ATARM-04-May-09 37.6.8 UDP Interrupt Clear Register Register Name:UDP_ICR Access Type: Write-only 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 WAKEUP 5 - 28 - 20 - 12 ENDBUSRES 4 - 27 - 19 - 11 SOFINT 3 - 26 - 18 - 10 EXTRSM 2 - 25 - 17 - 9 RXRSM 1 - 24 - 16 - 8 RXSUSP 0 - * RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt. * RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt. * EXTRSM: Clear UDP External Resume Interrupt 0 = No effect. 1 = Clears UDP External Resume Interrupt. * SOFINT: Clear Start Of Frame Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt. * ENDBUSRES: Clear End of Bus Reset Interrupt 0 = No effect. 1 = Clears End of Bus Reset Interrupt. * WAKEUP: Clear Wakeup Interrupt 0 = No effect. 1 = Clears Wakeup Interrupt. 700 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 37.6.9 UDP Reset Endpoint Register Register Name:UDP_RST_EP Access Type: Read-write 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 EP5 28 - 20 - 12 - 4 EP4 27 - 19 - 11 - 3 EP3 26 - 18 - 10 - 2 EP2 25 - 17 - 9 - 1 EP1 24 - 16 - 8 - 0 EP0 * EP0: Reset Endpoint 0 * EP1: Reset Endpoint 1 * EP2: Reset Endpoint 2 * EP3: Reset Endpoint 3 * EP4: Reset Endpoint 4 * EP5: Reset Endpoint 5 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter 5.8.5 in the USB Serial Bus Specification, Rev.2.0. Warning: This flag must be cleared at the end of the reset. It does not clear UDP_CSRx flags. 0 = No reset. 1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_CSRx register. Resetting the endpoint is a two-step operation: 1. Set the corresponding EPx field. 2. Clear the corresponding EPx field. 701 6384D-ATARM-04-May-09 37.6.10 UDP Endpoint Control and Status Register Register Name:UDP_CSRx [x = 0..5] Access Type: Read-write 31 - 23 30 - 22 29 - 21 28 - 20 RXBYTECNT 15 EPEDS 7 DIR 14 - 6 RX_DATA_ BK1 13 - 5 FORCE STALL 12 - 4 TXPKTRDY 11 DTGLE 3 STALLSENT ISOERROR 10 9 EPTYPE 1 RX_DATA_ BK0 8 27 - 19 26 25 RXBYTECNT 17 24 18 16 2 RXSETUP 0 TXCOMP WARNING: Due to synchronization between MCK and UDPCK, the software application must wait for the end of the write operation before executing another write by polling the bits which must be set/cleared. //! Clear flags of UDP UDP_CSR register and waits for synchronization #define Udp_ep_clr_flag(pInterface, endpoint, flags) { \ pInterface->UDP_CSR[endpoint] &= ~(flags); \ while ( (pInterface->UDP_CSR[endpoint] & (flags)) == (flags) ); \ } //! Set flags of UDP UDP_CSR register and waits for synchronization #define Udp_ep_set_flag(pInterface, endpoint, flags) { \ pInterface->UDP_CSR[endpoint] |= (flags); \ while ( (pInterface->UDP_CSR[endpoint] & (flags)) != (flags) ); \ } Note: In a preemptive environment, set or clear the flag and wait for a time of 1 UDPCK clock cycle and 1peripheral clock cycle. However, RX_DATA_BLK0, TXPKTRDY, RX_DATA_BK1 require wait times of 3 UDPCK clock cycles and 3 peripheral clock cycles before accessing DPR. * TXCOMP: Generates an IN Packet with Data Previously Written in the DPR This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Clear the flag, clear the interrupt. 1 = No effect. Read (Set by the USB peripheral): 0 = Data IN transaction has not been acknowledged by the Host. 1 = Data IN transaction is achieved, acknowledged by the Host. After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction. 702 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 0. 1 = A data packet has been received, it has been stored in the FIFO's Bank 0. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. * RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transaction is not accepted while RXSETUP is set. * STALLSENT: Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) This flag generates an interrupt while it is set to one. STALLSENT: This ends a STALL handshake. Read: 0 = The host has not acknowledged a STALL. 1 = Host has acknowledged the stall. Write: 0 = Resets the STALLSENT flag, clears the interrupt. 1 = No effect. 703 6384D-ATARM-04-May-09 This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0 = No error in the previous isochronous transfer. 1 = CRC error has been detected, data available in the FIFO are corrupted. Write: 0 = Resets the ISOERROR flag, clears the interrupt. 1 = No effect. * TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0 = There is no data to send. 1 = The data is waiting to be sent upon reception of token IN. Write: 0 = Can be used in the procedure to cancel transmission data. (See, Section 37.5.2.9 "Transmit Data Cancellation" on page 685) 1 = A new data payload has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. * FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0 = Normal state. 1 = Stall state. Write: 0 = Return to normal state. 1 = Send STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request. 704 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Bulk and interrupt endpoints: This bit notifies the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag. * RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notifies USB device that data have been read in the FIFO's Bank 1. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. * DIR: Transfer Direction (only available for control endpoints) Read-write 0 = Allows Data OUT transactions in the control data stage. 1 = Enables Data IN transactions in the control data stage. Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage. This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage. * EPTYPE[2:0]: Endpoint Type Read-write 000 001 101 010 110 011 111 Control Isochronous OUT Isochronous IN Bulk OUT Bulk IN Interrupt OUT Interrupt IN 705 6384D-ATARM-04-May-09 * DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. * EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint. Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints. Note: After reset, all endpoints are configured as control endpoints (zero). * RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx register. 706 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 37.6.11 UDP FIFO Data Register Register Name:UDP_FDRx [x = 0..5] Access Type: Read-write 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FIFO_DATA 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx register is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. 707 6384D-ATARM-04-May-09 37.6.12 UDP Transceiver Control Register Register Name:UDP_TXVC Access Type: Read-write 31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 PUON 1 - 24 - 16 - 8 TXVDIS 0 - WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register. * TXVDIS: Transceiver Disable When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can be done by setting TXVDIS field. To enable the transceiver, TXVDIS must be cleared. * PUON: Pullup On 0: The 1.5K integrated pullup on DP is disconnected. 1: The 1.5 K integrated pullup on DP is connected. NOTE: If the USB pullup is not connected on DP, the user should not write in any UDP register other than the UDP_TXVC register. This is because if DP and DM are floating at 0, or pulled down, then SE0 is received by the device with the consequence of a USB Reset. 708 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 38. USB Host Port (UHP) 38.1 Overview The USB Host Port (UHP) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols. The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several high-speed half-duplex serial communication ports at a baud rate of 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.) and the USB hub can be connected to the USB host in the USB "tiered star" topology. The USB Host Port controller is fully compliant with the Open HCI specification. The USB Host Port User Interface (registers description) can be found in the Open HCI Rev 1.0 Specification available on http://h18000.www1.hp.com/productinfo/development/openhci.html. The standard OHCI USB stack driver can be easily ported to Atmel's architecture in the same way all existing class drivers run without hardware specialization. This means that all standard class devices are automatically detected and available to the user application. As an example, integrating an HID (Human Interface Device) class driver provides a plug & play feature for all USB keyboards and mouses. 38.2 Block Diagram Figure 38-1. Block Diagram AHB HCI Slave Block OHCI Registers Control List Processor Block ED & TD Regsisters OHCI Root Hub Registers Embedded USB v2.0 Full-speed Transceiver USB transceiver USB transceiver DP DM DP DM Slave Root Hub and Host SIE PORT S/M PORT S/M AHB HCI Master Block Master Data FIFO 64 x 8 uhp_int MCK UHPCK Access to the USB host operational registers is achieved through the AHB bus slave interface. The Open HCI host controller initializes master DMA transfers through the ASB bus master interface as follows: * Fetches endpoint descriptors and transfer descriptors * Access to endpoint data from system memory 709 6384D-ATARM-04-May-09 * Access to the HC communication area * Write status and retire transfer Descriptor Memory access errors (abort, misalignment) lead to an "Unrecoverable Error" indicated by the corresponding flag in the host controller operational registers. The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of downstream ports can be determined by the software driver reading the root hub's operational registers. Device connection is automatically detected by the USB host port logic. USB physical transceivers are integrated in the product and driven by the root hub's ports. Over current protection on ports can be activated by the USB host controller. Atmel's standard product does not dedicate pads to external over current protection. 38.3 38.3.1 Product Dependencies I/O Lines DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceivers are controlled by the USB host controller. 38.3.2 Power Management The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy of 0.25%. Thus the USB device peripheral receives two clocks from the Power Management Controller (PMC): the master clock MCK used to drive the peripheral user interface (MCK domain) and the UHPCLK 48 MHz clock used to interface with the bus USB signals (Recovered 12 MHz domain). 38.3.3 Interrupt The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling USB host interrupts requires programming the AIC before configuring the UHP. 38.4 Functional Description Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a. 38.4.1 Host Controller Interface There are two communication channels between the Host Controller and the Host Controller Driver. The first channel uses a set of operational registers located on the USB Host Controller. The Host Controller is the target for all communications on this channel. The operational registers contain control, status and list pointer registers. They are mapped in the memory mapped area. Within the operational register set there is a pointer to a location in the processor address space named the Host Controller Communication Area (HCCA). The HCCA is the second communication channel. The host controller is the master for all communication on this channel. The HCCA contains the head pointers to the interrupt Endpoint Descriptor lists, the head pointer to the done queue and status information associated with start-of-frame processing. The basic building blocks for communication across the interface are Endpoint Descriptors (ED, 4 double words) and Transfer Descriptors (TD, 4 or 8 double words). The host controller assigns 710 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary an Endpoint Descriptor to each endpoint in the system. A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific endpoint. Figure 38-2. USB Host Communication Channels Device Enumeration Open HCI Operational Registers Mode HCCA Status Event Frame Int Ratio Control Bulk Host Controller Communications Area Interrupt 0 Interrupt 1 Interrupt 2 ... Interrupt 31 ... ... Done Device Register in Memory Space Shared RAM = Transfer Descriptor = Endpoint Descriptor 38.4.2 Host Controller Driver Figure 38-3. USB Host Drivers User Application User Space Kernel Drivers Mini Driver Class Driver Class Driver HUB Driver USB Driver Host Controller Driver Hardware Host Controller Hardware USB Handling is done through several layers as follows: 711 6384D-ATARM-04-May-09 * Host controller hardware and serial engine: Transmits and receives USB data on the bus. * Host controller driver: Drives the Host controller hardware and handles the USB protocol. * USB Bus driver and hub driver: Handles USB commands and enumeration. Offers a hardware independent interface. * Mini driver: Handles device specific commands. * Class driver: Handles standard devices. This acts as a generic driver for a class of devices, for example the HID driver. 38.5 Typical Connection Figure 38-4. Board Schematic to Interface UHP Device Controller 5V 0.20A Type A Connector 10F HDMA or HDMB HDPA or HDPB 100nF 10nF REXT REXT A termination serial resistor must be connected to HDP and HDM. The resistor value is defined in the electrical specification of the product (REXT). 712 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 39. Image Sensor Interface (ISI) 39.1 Overview The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats. It does data conversion, if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities. In grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the LCD controller. Internal FIFOs on the preview and codec paths are used to store the incoming data. The RGB output on the preview path is compatible with the LCD controller. This module outputs the data in RGB format (LCD compatible) and has scaling capabilities to make it compliant to the LCD display resolution (See Table 39-3 on page 716). Several input formats such as preprocessed RGB or YCbCr are supported through the data bus interface. It supports two modes of synchronization: 1. The hardware with ISI_VSYNC and ISI_HSYNC signals 2. The International Telecommunication Union Recommendation ITU-R BT.656-4 Start-ofActive-Video (SAV) and End-of-Active-Video (EAV) synchronization sequence. Using EAV/SAV for synchronization reduces the pin count (ISI_VSYNC, ISI_HSYNC not used). The polarity of the synchronization pulse is programmable to comply with the sensor signals. Table 39-1. Signal ISI_VSYNC ISI_HSYNC ISI_DATA[11..0] ISI_MCK ISI_PCK I/O Description Dir IN IN IN OUT IN Description Vertical Synchronization Horizontal Synchronization Sensor Pixel Data Master Clock Provided to the Image Sensor Pixel Clock Provided by the Image Sensor Figure 39-1. ISI Connection Example Image Sensor Image Sensor Interface data[11..0] CLK PCLK VSYNC HSYNC ISI_DATA[11..0] ISI_MCK ISI_PCK ISI_VSYNC ISI_HSYNC 713 6384D-ATARM-04-May-09 39.2 Block Diagram Figure 39-2. Image Sensor Interface Block Diagram APB bus AHB bus Hsync/Len Vsync/Fen Timing Signals Interface Camera Interrupt Controller From Rx buffers Config Registers Camera Interrupt Request Line APB Interface CCIR-656 Embedded Timing Decoder(SAV/EAV) CMOS sensor Pixel input up to 12 bit YCbCr 4:2:2 8:8:8 RGB 5:6:5 APB Clock Domain AHB Clock Domain Camera AHB Master Interface Scatter Mode Support Pixel Clock Domain Frame Rate Clipping + Color Conversion YCC to RGB 2-D Image Scaler Pixel Formatter Pixel Sampling Module Rx Direct Display FIFO Core Video Arbiter CMOS sensor pixel clock input Clipping + Color Conversion RGB to YCC Packed Formatter Rx Direct Capture FIFO codec_on 39.3 Functional Description The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus. This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock. The reduced pin count alternative for synchronization is supported for sensors that embed SAV (start of active video) and EAV (end of active video) delimiters in the data stream. The Image Sensor Interface interrupt line is generally connected to the Advanced Interrupt Controller and can trigger an interrupt at the beginning of each frame and at the end of a DMA frame transfer. If the SAV/EAV synchronization is used, an interrupt can be triggered on each delimiter event. For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr 4:2:2, RGB 8:8:8, RGB 5:6:5 and may be processed before the storage in memory. The data stream may be sent on both preview path and codec path if the bit CODEC_ON in the ISI_CR1 is one. To optimize the bandwidth, the codec path should be enabled only when a capture is required. In grayscale mode, the input data stream is stored in memory without any processing. The 12-bit data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the GS_MODE bit in the ISI_CR2 register. The codec datapath is not available when grayscale image is selected. A frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames. 714 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 39.3.1 Data Timing The two data timings using horizontal and vertical synchronization and EAV/SAV sequence synchronization are shown in Figure 39-3 and Figure 39-4. In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the pixel clock (ISI_PCK), after SFD lines of vertical blanking and SLD pixel clock periods delay programmed in the control register. The ITU-RBT.656-4 defines the functional timing for an 8-bit wide interface. There are two timing reference signals, one at the beginning of each video data block SAV (0xFF000080) and one at the end of each video data block EAV(0xFF00009D). Only data sent between EAV and SAV is captured. Horizontal blanking and vertical blanking are ignored. Use of the SAV and EAV synchronization eliminates the ISI_VSYNC and ISI_HSYNC signals from the interface, thereby reducing the pin count. In order to retrieve both frame and line synchronization properly, at least one line of vertical blanking is mandatory. Figure 39-3. HSYNC and VSYNC Synchronization Frame ISI_VSYNC 1 line ISI_HSYNC ISI_PCK DATA[7..0] Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Figure 39-4. SAV and EAV Sequence Synchronization ISII_PCK DATA[7..0] FF 00 00 SAV 80 Y Cb Y Cr Y Cb Y Cr Active Video Y Y Cr Y Cb FF 00 00 EAV 9D 715 6384D-ATARM-04-May-09 39.3.2 Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding. All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. Table 39-2. Mode Default Mode1 Mode2 Mode3 Data Ordering in YCbCr Mode Byte 0 Cb(i) Cr(i) Y(i) Y(i) Byte 1 Y(i) Y(i) Cb(i) Cr(i) Byte 2 Cr(i) Cb(i) Y(i+1) Y(i+1) Byte 3 Y(i+1) Y(i+1) Cr(i) Cb(i) Table 39-3. Mode RGB Format in Default Mode, RGB_CFG = 00, No Swap Byte Byte 0 Byte 1 D7 R7(i) G7(i) B7(i) R7(i+1) R4(i) G2(i) R4(i+1) G2(i+1) D6 R6(i) G6(i) B6(i) R6(i+1) R3(i) G1(i) R3(i+1) G1(i+1) D5 R5(i) G5(i) B5(i) R5(i+1) R2(i) G0(i) R2(i+1) G0(i+1) D4 R4(i) G4(i) B4(i) R4(i+1) R1(i) B4(i) R1(i+1) B4(i+1) D3 R3(i) G3(i) B3(i) R3(i+1) R0(i) B3(i) R0(i+1) B3(i+1) D2 R2(i) G2(i) B2(i) R2(i+1) G5(i) B2(i) G5(i+1) B2(i+1) D1 R1(i) G1(i) B1(i) R1(i+1) G4(i) B1(i) G4(i+1) B1(i+1) D0 R0(i) G0(i) B0(i) R0(i+1) G3(i) B0(i) G3(i+1) B0(i+1) RGB 8:8:8 Byte 2 Byte 3 Byte 0 Byte 1 RGB 5:6:5 Byte 2 Byte 3 Table 39-4. Mode RGB Format, RGB_CFG = 10 (Mode 2), No Swap Byte Byte 0 Byte 1 D7 G2(i) B4(i) G2(i+1) B4(i+1) D6 G1(i) B3(i) G1(i+1) B3(i+1) D5 G0(i) B2(i) G0(i+1) B2(i+1) D4 R4(i) B1(i) R4(i+1) B1(i+1) D3 R3(i) B0(i) R3(i+1) B0(i+1) D2 R2(i) G5(i) R2(i+1) G5(i+1) D1 R1(i) G4(i) R1(i+1) G4(i+1) D0 R0(i) G3(i) R0(i+1) G3(i+1) RGB 5:6:5 Byte 2 Byte 3 716 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 39-5. Mode RGB Format in Default Mode, RGB_CFG = 00, Swap Activated Byte Byte 0 Byte 1 D7 R0(i) G0(i) B0(i) R0(i+1) G3(i) B0(i) G3(i+1) B0(i+1) D6 R1(i) G1(i) B1(i) R1(i+1) G4(i) B1(i) G4(i+1) B1(i+1) D5 R2(i) G2(i) B2(i) R2(i+1) G5(i) B2(i) G5(i+1) B2(i+1) D4 R3(i) G3(i) B3(i) R3(i+1) R0(i) B3(i) R0(i+1) B3(i+1) D3 R4(i) G4(i) B4(i) R4(i+1) R1(i) B4(i) R1(i+1) B4(i+1) D2 R5(i) G5(i) B5(i) R5(i+1) R2(i) G0(i) R2(i+1) G0(i+1) D1 R6(i) G6(i) B6(i) R6(i+1) R3(i) G1(i) R3(i+1) G1(i+1) D0 R7(i) G7(i) B7(i) R7(i+1) R4(i) G2(i) R4(i+1) G2(i+1) RGB 8:8:8 Byte 2 Byte 3 Byte 0 Byte 1 RGB 5:6:5 Byte 2 Byte 3 The RGB 5:6:5 input format is processed to be displayed as RGB 5:5:5 format, compliant with the 16-bit mode of the LCD controller. 39.3.3 Clocks The sensor master clock (ISI_MCK) can be generated either by the Advanced Power Management Controller (APMC) through a Programmable Clock output or by an external oscillator connected to the sensor. None of the sensors embeds a power management controller, so providing the clock by the APMC is a simple and efficient way to control power consumption of the system. Care must be taken when programming the system clock. The ISI has two clock domains, the system bus clock and the pixel clock provided by sensor. The two clock domains are not synchronized, but the system clock must be faster than pixel clock. 717 6384D-ATARM-04-May-09 39.3.4 39.3.4.1 Preview Path Scaling, Decimation (Subsampling) This module resizes captured 8-bit color sensor images to fit the LCD display format. The resize module performs only downscaling. The same ratio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. The decimation factor is a multiple of 1/16 and values 0 to 15 are forbidden. Table 39-6. Dec value Dec Factor Decimation Factor 0->15 X 16 1 17 1.063 18 1.125 19 1.188 ... ... 124 7.750 125 7.813 126 7.875 127 7.938 Table 39-7. OUTPUT VGA 640*480 QVGA 320*240 CIF 352*288 QCIF 176*144 Decimation and Scaler Offset Values INPUT 352*288 NA 16 16 16 640*480 16 32 26 53 800*600 20 40 33 66 1280*1024 32 64 56 113 1600*1200 40 80 66 133 2048*1536 51 102 85 170 F F F F Example: Input 1280*1024 Output=640*480 Hratio = 1280/640 =2 Vratio = 1024/480 =2.1333 The decimation factor is 2 so 32/16. 718 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 39-5. Resize Examples 1280 32/16 decimation 640 1024 480 1280 56/16 decimation 352 1024 288 39.3.4.2 Color Space Conversion This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable: C0 0 C1 Y - Y off R = C 0 - C 2 - C 3 x C b - C boff G B C0 C4 0 C r - C roff Example of programmable value to convert YCrCb to RGB: R = 1,164 ( Y - 16 ) + 1,596 ( C r - 128 ) G = 1,164 ( Y - 16 ) - 0,813 ( C r - 128 ) - 0,392 ( C b - 128 ) B = 1,164 ( Y - 16 ) + 2,107 ( C b - 128 ) An example of programmable value to convert from YUV to RGB: R = Y + 1,596 V G = Y - 0,394 U - 0,436 V B = Y + 2,032 U 719 6384D-ATARM-04-May-09 39.3.4.3 Memory Interface Preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:5:5 format compliant with 16-bit format of the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, formatter module discards the lower-order bits. Example: Converting from RGB 8:8:8 to RGB 5:6:5, it discards the three LSBs from the red and blue channels, and two LSBs from the green channel. When grayscale mode is enabled, two memory format are supported. One mode supports 2 pixels per word, and the other mode supports 1 pixel per word. Table 39-8. GS_MODE 0 1 Grayscale Memory Mapping Configuration for 12-bit Data DATA[31:24] P_0[11:4] P_0[11:4] DATA[23:16] P_0[3:0], 0000 P_0[3:0], 0000 DATA[15:8] P_1[11:4] 0 DATA[7:0] P_1[3:0], 0000 0 39.3.4.4 FIFO and DMA Features Both preview and Codec datapaths contain FIFOs, asynchronous buffers that are used to safely transfer formatted pixels from Pixel clock domain to AHB clock domain. A video arbiter is used to manage FIFO thresholds and triggers a relevant DMA request through the AHB master interface. Thus, depending on FIFO state, a specified length burst is asserted. Regarding AHB master interface, it supports Scatter DMA mode through linked list operation. This mode of operation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. The destination frame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each FBD controls the transfer of one entire frame and then optionally loads a further FBD to switch the DMA operation at another frame buffer address. The FBD is defined by a series of two words. The first one defines the current frame buffer address, and the second defines the next FBD memory location. This DMA transfer mode is only available for preview datapath and is configured in the ISI_PPFBD register that indicates the memory location of the first FBD. The primary FBD is programmed into the camera interface controller. The data to be transferred described by an FBD requires several burst access. In the example below, the use of 2 pingpong frame buffers is described. Example The first FBD, stored at address 0x30000, defines the location of the first frame buffer. Destination Address: frame buffer ID0 0x02A000 Next FBD address: 0x30010 Second FBD, stored at address 0x30010, defines the location of the second frame buffer. Destination Address: frame buffer ID1 0x3A000 Transfer width: 32 bit Next FBD address: 0x30000, wrapping to first FBD. Using this technique, several frame buffers can be configured through the linked list. Figure 39-6 illustrates a typical three frame buffer application. Frame n is mapped to frame buffer 0, frame n+1 is mapped to frame buffer 1, frame n+2 is mapped to Frame buffer 2, further frames wrap. A codec request occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory space. 720 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 39-6. Three Frame Buffers Application and Memory Mapping Codec Request Codec Done frame n-1 frame n frame n+1 frame n+2 frame n+3 frame n+4 Memory Space Frame Buffer 3 Frame Buffer 0 LCD Frame Buffer 1 ISI config Space 4:2:2 Image Full ROI 39.3.5 39.3.5.1 Codec Path Color Space Conversion Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module. If the RGB input stream is selected, this module converts RGB to YCrCb color space with the formulas given below: Y Cr = Cb Y off R C 3 - C 4 - C 5 x G + Cr off B -C6 -C7 C8 Cb off C0 C1 C2 An example of coefficients is given below: Y = 0,257 R + 0,504 G + 0,098 B + 16 C = 0,439 R - 0,368 G - 0,071 B + 128 r C = - 0,148 R - 0,291 G + 0,439 B + 128 b 721 6384D-ATARM-04-May-09 39.3.5.2 Memory Interface Dedicated FIFO are used to support packed memory mapping. YCrCb pixel components are sent in a single 32-bit word in a contiguous space (packed). Data is stored in the order of natural scan lines. Planar mode is not supported. DMA Features Unlike preview datapath, codec datapath DMA mode does not support linked list operation. Only the CODEC_DMA_ADDR register is used to configure the frame buffer base address. 39.3.5.3 722 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 39.4 Image Sensor Interface (ISI) User Interface ISI Memory Mapping Register ISI Control 1 Register ISI Control 2 Register ISI Status Register ISI Interrupt Enable Register ISI Interrupt Disable Register ISI Interrupt Mask Register Reserved Reserved ISI Preview Size Register ISI Preview Decimation Factor Register ISI Preview Primary FBD Register ISI Codec DMA Base Address Register ISI CSC YCrCb To RGB Set 0 Register ISI CSC YCrCb To RGB Set 1 Register ISI CSC RGB To YCrCb Set 0 Register ISI CSC RGB To YCrCb Set 1 Register ISI CSC RGB To YCrCb Set 2 Register Reserved Reserved Register ISI_CR1 ISI_CR2 ISI_SR ISI_IER ISI_IDR ISI_IMR ISI_PSIZE ISI_PDECF ISI_PPFBD ISI_CDBA ISI_Y2R_SET0 ISI_Y2R_SET1 ISI_R2Y_SET0 ISI_R2Y_SET1 ISI_R2Y_SET2 - - Access Read-write Read-write Read Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write Read-write - - Reset 0x00000002 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000010 0x00000000 0x00000000 0x6832cc95 0x00007102 0x01324145 0x01245e38 0x01384a4b - - Table 39-9. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44-0xF8 0xFC Note: Several parts of the ISI controller use the pixel clock provided by the image sensor (ISI_PCK). Thus the user must first program the image sensor to provide this clock (ISI_PCK) before programming the Image Sensor Controller. 723 6384D-ATARM-04-May-09 39.4.1 ISI Control 1 Register Register Name: ISI_CR1 Access Type: Read-write Reset Value: 0x00000002 31 30 29 28 SFD 23 22 21 20 SLD 15 CODEC_ON 7 CRC_SYNC 14 THMASK 6 EMB_SYNC 5 13 12 FULL 4 PIXCLK_POL 11 3 VSYNC_POL 10 9 FRATE 1 ISI_DIS 8 19 18 17 16 27 26 25 24 2 HSYNC_POL 0 ISI_RST * ISI_RST: Image Sensor Interface Reset Write-only. Refer to bit SOFTRST in Section 39.4.3 "ISI Status Register" on page 728 for soft reset status. 0: No action 1: Resets the image sensor interface. * ISI_DIS: Image Sensor Disable: 0: Enable the image sensor interface. 1: Finish capturing the current frame and then shut down the module. * HSYNC_POL: Horizontal Synchronization Polarity 0: HSYNC active high 1: HSYNC active low * VSYNC_POL: Vertical sYnchronization Polarity 0: VSYNC active high 1: VSYNC active low * PIXCLK_POL: Pixel Clock Polarity 0: Data is sampled on rising edge of pixel clock 1: Data is sampled on falling edge of pixel clock * EMB_SYNC: Embedded Synchronization 0: Synchronization by HSYNC, VSYNC 1: Synchronization by embedded synchronization sequence SAV/EAV * CRC_SYNC: Embedded Synchronization 0: No CRC correction is performed on embedded synchronization 724 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 1: CRC correction is performed. if the correction is not possible, the current frame is discarded and the CRC_ERR is set in the status register. * FRATE: Frame Rate [0..7] 0: All the frames are captured, else one frame every FRATE+1 is captured. * FULL: Full Mode is Allowed 1: Both codec and preview datapaths are working simultaneously * THMASK: Threshold Mask 0: 4, 8 and 16 AHB bursts are allowed 1: 8 and 16 AHB bursts are allowed 2: Only 16 AHB bursts are allowed * CODEC_ON: Enable the Codec Path Enable Bit Write-only. 0: The codec path is disabled 1: The codec path is enabled and the next frame is captured. Refer to bit CDC_PND in "ISI Status Register" on page 728. * SLD: Start of Line Delay SLD pixel clock periods to wait before the beginning of a line. * SFD: Start of Frame Delay SFD lines are skipped at the beginning of the frame. 725 6384D-ATARM-04-May-09 39.4.2 ISI Control 2 Register Register Name: ISI_CR2 Access Type: Read-write Reset Value: 0x0 31 RGB_CFG 23 22 21 30 29 YCC_SWAP 20 IM_HSIZE 15 COL_SPACE 7 14 RGB_SWAP 6 13 GRAYSCALE 5 12 RGB_MODE 4 IM_VSIZE 11 GS_MODE 3 10 9 IM_VSIZE 1 8 28 27 19 26 25 IM_HSIZE 17 24 18 16 2 0 * IM_VSIZE: Vertical Size of the Image Sensor [0..2047] Vertical size = IM_VSIZE + 1 * GS_MODE 0: 2 pixels per word 1: 1 pixel per word * RGB_MODE: RGB Input Mode 0: RGB 8:8:8 24 bits 1: RGB 5:6:5 16 bits * GRAYSCALE 0: Grayscale mode is disabled 1: Input image is assumed to be grayscale coded * RGB_SWAP 0: D7 -> R7 1: D0 -> R7 The RGB_SWAP has no effect when the grayscale mode is enabled. * COL_SPACE: Color Space for The Image Data 0: YCbCr 1: RGB * IM_HSIZE: Horizontal Size of the Image Sensor [0..2047] Horizontal size = IM_HSIZE + 1 726 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * YCC_SWAP: Defines the YCC Image Data YCC_SWAP 00: Default 01: Mode1 10: Mode2 11: Mode3 Byte 0 Cb(i) Cr(i) Y(i) Y(i) Byte 1 Y(i) Y(i) Cb(i) Cr(i) Byte 2 Cr(i) Cb(i) Y(i+1) Y(i+1) Byte 3 Y(i+1) Y(i+1) Cr(i) Cb(i) * RGB_CFG: Defines RGB Pattern when RGB_MODE is set to 1 RGB_CFG 00: Default 01: Mode1 10: Mode2 11: Mode3 Byte 0 R/G(MSB) B/G(MSB) G(LSB)/R G(LSB)/B Byte 1 G(LSB)/B G(LSB)/R B/G(MSB) R/G(MSB) Byte 2 R/G(MSB) B/G(MSB) G(LSB)/R G(LSB)/B Byte 3 G(LSB)/B G(LSB)/R B/G(MSB) R/G(MSB) If RGB_MODE is set to RGB 8:8:8, then RGB_CFG = 0 implies RGB color sequence, else it implies BGR color sequence. 727 6384D-ATARM-04-May-09 39.4.3 ISI Status Register Register Name: ISI_SR Access Type: Read Reset Value: 0x0 31 - 23 - 15 - 7 FO_P_EMP 30 - 22 - 14 - 6 FO_P_OVF 29 - 21 - 13 - 5 FO_C_OVF 28 - 20 - 12 - 4 CRC_ERR 27 - 19 - 11 - 3 CDC_PND 26 - 18 - 10 - 2 SOFTRST 25 - 17 - 9 FR_OVR 1 DIS 24 - 16 - 8 FO_C_EMP 0 SOF * SOF: Start of Frame 0: No start of frame has been detected. 1: A start of frame has been detected. * DIS: Image Sensor Interface Disable 0: The image sensor interface is enabled. 1: The image sensor interface is disabled and stops capturing data. The DMA controller and the core can still read the FIFOs. * SOFTRST: Software Reset 0: Software reset not asserted or not completed. 1: Software reset has completed successfully. * CDC_PND: Codec Request Pending 0: No request asserted. 1: A codec request is pending. If a codec request is asserted during a frame, the CDC_PND bit rises until the start of a new frame. The capture is completed when the flag FO_C_EMP = 1. * CRC_ERR: CRC Synchronization Error 0: No CRC error in the embedded synchronization frame (SAV/EAV) 1: The CRC_SYNC is enabled in the control register and an error has been detected and not corrected. The frame is discarded and the ISI waits for a new one. * FO_C_OVF: FIFO Codec Overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. 728 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * FO_P_OVF: FIFO Preview Overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. * FO_P_EMP 0:The DMA has not finished transferring all the contents of the preview FIFO. 1:The DMA has finished transferring all the contents of the preview FIFO. * FO_C_EMP 0: The DMA has not finished transferring all the contents of the codec FIFO. 1: The DMA has finished transferring all the contents of the codec FIFO. * FR_OVR: Frame Rate Overrun 0: No frame overrun. 1: Frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing FIFOs. 729 6384D-ATARM-04-May-09 39.4.4 Interrupt Enable Register Register Name: ISI_IER Access Type: Read-write Reset Value: 0x0 31 - 23 - 15 - 7 FO_P_EMP 30 - 22 - 14 - 6 FO_P_OVF 29 - 21 - 13 - 5 FO_C_OVF 28 - 20 - 12 - 4 CRC_ERR 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 SOFTRST 25 - 17 - 9 FR_OVR 1 DIS 24 - 16 - 8 FO_C_EMP 0 SOF * SOF: Start of Frame 1: Enables the Start of Frame interrupt. * DIS: Image Sensor Interface Disable 1: Enables the DIS interrupt. * SOFTRST: Soft Reset 1: Enables the Soft Reset Completion interrupt. * CRC_ERR: CRC Synchronization Error 1: Enables the CRC_SYNC interrupt. * FO_C_OVF: FIFO Codec Overflow 1: Enables the codec FIFO overflow interrupt. * FO_P_OVF: FIFO Preview Overflow 1: Enables the preview FIFO overflow interrupt. * FO_P_EMP 1: Enables the preview FIFO empty interrupt. * FO_C_EMP 1: Enables the codec FIFO empty interrupt. * FR_OVR: Frame Overrun 1: Enables the Frame overrun interrupt. 730 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 39.4.5 ISI Interrupt Disable Register Register Name: ISI_IDR Access Type: Read-write Reset Value: 0x0 31 - 23 - 15 - 7 FO_P_EMP 30 - 22 - 14 - 6 FO_P_OVF 29 - 21 - 13 - 5 FO_C_OVF 28 - 20 - 12 - 4 CRC_ERR 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 SOFTRST 25 - 17 - 9 FR_OVR 1 DIS 24 - 16 - 8 FO_C_EMP 0 SOF * SOF: Start of Frame 1: Disables the Start of Frame interrupt. * DIS: Image Sensor Interface Disable 1: Disables the DIS interrupt. * SOFTRST 1: Disables the soft reset completion interrupt. * CRC_ERR: CRC Synchronization Error 1: Disables the CRC_SYNC interrupt. * FO_C_OVF: FIFO Codec Overflow 1: Disables the codec FIFO overflow interrupt. * FO_P_OVF: FIFO Preview Overflow 1: Disables the preview FIFO overflow interrupt. * FO_P_EMP 1: Disables the preview FIFO empty interrupt. * FO_C_EMP 1: Disables the codec FIFO empty interrupt. * FR_OVR 1: Disables frame overrun interrupt. 731 6384D-ATARM-04-May-09 39.4.6 ISI Interrupt Mask Register Register Name: ISI_IMR Access Type: Read-write Reset Value: 0x0 31 - 23 - 15 - 7 FO_P_EMP 30 - 22 - 14 - 6 FO_P_OVF 29 - 21 - 13 - 5 FO_C_OVF 28 - 20 - 12 - 4 CRC_ERR 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 SOFTRST 25 - 17 - 9 FR_OVR 1 DIS 24 - 16 - 8 FO_C_EMP 0 SOF * SOF: Start of Frame 0: The Start of Frame interrupt is disabled. 1: The Start of Frame interrupt is enabled. * DIS: Image Sensor Interface Disable 0: The DIS interrupt is disabled. 1: The DIS interrupt is enabled. * SOFTRST 0: The soft reset completion interrupt is enabled. 1: The soft reset completion interrupt is disabled. * CRC_ERR: CRC Synchronization Error 0: The CRC_SYNC interrupt is disabled. 1: The CRC_SYNC interrupt is enabled. * FO_C_OVF: FIFO Codec Overflow 0: The codec FIFO overflow interrupt is disabled. 1: The codec FIFO overflow interrupt is enabled. * FO_P_OVF: FIFO Preview Overflow 0: The preview FIFO overflow interrupt is disabled. 1: The preview FIFO overflow interrupt is enabled. * FO_P_EMP 0: The preview FIFO empty interrupt is disabled. 1: The preview FIFO empty interrupt is enabled. 732 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * FO_C_EMP 0: The codec FIFO empty interrupt is disabled. 1: The codec FIFO empty interrupt is enabled. * FR_OVR: Frame Rate Overrun 0: The frame overrun interrupt is disabled. 1: The frame overrun interrupt is enabled. 733 6384D-ATARM-04-May-09 39.4.7 ISI Preview Register Register Name: ISI_PSIZE Access Type: Read-write Reset Value: 0x0 31 - 23 30 - 22 29 - 21 28 - 20 PREV_HSIZE 27 - 19 26 - 18 25 PREV_HSIZE 17 24 16 15 - 7 14 - 6 13 - 5 12 - 4 PREV_VSIZE 11 - 3 10 - 2 9 PREV_VSIZE 1 8 0 * PREV_VSIZE: Vertical Size for the Preview Path Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode). * PREV_HSIZE: Horizontal Size for the Preview Path Horizontal Preview size = PREV_HSIZE + 1 (640 max only in RGB mode). 734 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 39.4.8 ISI Preview Decimation Factor Register Register Name: ISI_PDECF Access Type: Read-write Reset Value: 0x00000010 31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 DEC_FACTOR * DEC_FACTOR: Decimation Factor DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation. 735 6384D-ATARM-04-May-09 39.4.9 ISI Preview Primary FBD Register Register Name: ISI_PPFBD Access Type: Read-write Reset Value: 0x0 31 30 29 28 27 PREV_FBD_ADDR 20 19 PREV_FBD_ADDR 12 11 PREV_FBD_ADDR 4 3 PREV_FBD_ADDR 26 25 24 23 22 21 18 17 16 15 14 13 10 9 8 7 6 5 2 1 0 * PREV_FBD_ADDR: Base Address for Preview Frame Buffer Descriptor Written with the address of the start of the preview frame buffer queue, reads as a pointer to the current buffer being used. The frame buffer is forced to word alignment. 736 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 39.4.10 ISI Codec DMA Base Address Register Register Name: ISI_CDBA Access Type: Read-write Reset Value: 0x0 31 30 29 28 27 CODEC_DMA_ADDR 20 19 CODEC_DMA_ADDR 12 11 CODEC_DMA_ADDR 4 3 CODEC_DMA_ADDR 26 25 24 23 22 21 18 17 16 15 14 13 10 9 8 7 6 5 2 1 0 * CODEC_DMA_ADDR: Base Address for Codec DMA This register contains codec datapath start address of buffer location. 737 6384D-ATARM-04-May-09 39.4.11 ISI Color Space Conversion YCrCb to RGB Set 0 Register Register Name: ISI_Y2R_SET0 Access Type: Read-write Reset Value: 0x6832cc95 31 30 29 28 C3 27 26 25 24 23 22 21 20 C2 19 18 17 16 15 14 13 12 C1 11 10 9 8 7 6 5 4 C0 3 2 1 0 * C0: Color Space Conversion Matrix Coefficient C0 C0 element, default step is 1/128, ranges from 0 to 1.9921875. * C1: Color Space Conversion Matrix Coefficient C1 C1 element, default step is 1/128, ranges from 0 to 1.9921875. * C2: Color Space Conversion Matrix Coefficient C2 C2 element, default step is 1/128, ranges from 0 to 1.9921875. * C3: Color Space Conversion Matrix Coefficient C3 C3 element default step is 1/128, ranges from 0 to 1.9921875. 738 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 39.4.12 ISI Color Space Conversion YCrCb to RGB Set 1 Register Register Name: ISI_Y2R_SET1 Access Type: Read-write Reset Value: 0x00007102 31 - 23 - 15 - 30 - 22 - 14 Cboff 29 - 21 - 13 Croff 28 - 20 - 12 Yoff 27 - 19 - 11 - 26 - 18 - 10 - 25 - 17 - 9 - 24 - 16 - 8 C4 C4 * C4: Color Space Conversion Matrix Coefficient C4 C4 element default step is 1/128, ranges from 0 to 3.9921875. * Yoff: Color Space Conversion Luminance Default Offset 0: No offset. 1: Offset = 128. * Croff: Color Space Conversion Red Chrominance Default Offset 0: No offset. 1: Offset = 16. * Cboff: Color Space Conversion Blue Chrominance Default Offset 0: No offset. 1: Offset = 16. 739 6384D-ATARM-04-May-09 39.4.13 ISI Color Space Conversion RGB to YCrCb Set 0 Register Register Name: ISI_R2Y_SET0 Access Type: Read-write Reset Value: 0x01324145 31 - 23 30 - 22 29 - 21 28 - 20 C2 27 - 19 26 - 18 25 - 17 24 Roff 16 15 14 13 12 C1 11 10 9 8 7 6 5 4 C0 3 2 1 0 * C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/256, from 0 to 0.49609375. * C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, from 0 to 0.9921875. * C2: Color Space Conversion Matrix Coefficient C2 C2 element default step is 1/512, from 0 to 0.2480468875. * Roff: Color Space Conversion Red Component Offset 0: No offset. 1: Offset = 16. 740 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 39.4.14 ISI Color Space Conversion RGB to YCrCb Set 1 Register Register Name: ISI_R2Y_SET1 Access Type: Read-write Reset Value: 0x01245e38 31 - 23 30 - 22 29 - 21 28 - 20 C5 27 - 19 26 - 18 25 - 17 24 Goff 16 15 14 13 12 C4 11 10 9 8 7 6 5 4 C3 3 2 1 0 * C3: Color Space Conversion Matrix Coefficient C3 C0 element default step is 1/128, ranges from 0 to 0.9921875. * C4: Color Space Conversion Matrix Coefficient C4 C1 element default step is 1/256, ranges from 0 to 0.49609375. * C5: Color Space Conversion Matrix Coefficient C5 C1 element default step is 1/512, ranges from 0 to 0.2480468875. * Goff: Color Space Conversion Green Component Offset 0: No offset. 1: Offset = 128. 741 6384D-ATARM-04-May-09 39.4.15 ISI Color Space Conversion RGB to YCrCb Set 2 Register Register Name: ISI_R2Y_SET2 Access Type: Read-write Reset Value: 0x01384a4b 31 - 23 30 - 22 29 - 21 28 - 20 C8 27 - 19 26 - 18 25 - 17 24 Boff 16 15 14 13 12 C7 11 10 9 8 7 6 5 4 C6 3 2 1 0 * C6: Color Space Conversion Matrix Coefficient C6 C6 element default step is 1/512, ranges from 0 to 0.2480468875. * C7: Color Space Conversion Matrix coefficient C7 C7 element default step is 1/256, ranges from 0 to 0.49609375. * C8: Color Space Conversion Matrix Coefficient C8 C8 element default step is 1/128, ranges from 0 to 0.9921875. * Boff: Color Space Conversion Blue Component Offset 0: No offset. 1: Offset = 128. 742 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 40. Analog-to-digital Converter (ADC) 40.1 Overview The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It also integrates a 4-to-1 analog multiplexer, making possible the analog-to-digital conversions of 4 analog lines. The conversions extend from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are configurable. The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC channel. These features reduce both power consumption and processor intervention. Finally, the user can configure ADC timings, such as Startup Time and Sample & Hold Time. 40.2 Block Diagram Figure 40-1. Analog-to-Digital Converter Block Diagram Timer Counter Channels ADC Trigger Selection ADTRG Control Logic ADC Interrupt AIC VDDANA ADVREF ASB ADPDC Dedicated Analog Inputs ADUser Interface ADSuccessive Approximation Register Analog-to-Digital Converter APB Peripheral Bridge AD- Analog Inputs Multiplexed with I/O lines PIO AD- AD- GND 743 6384D-ATARM-04-May-09 40.3 Signal Description ADC Pin Description Description Analog power supply Reference voltage Analog input channels External trigger Table 40-1. Pin Name VDDANA ADVREF AD0 - AD3 ADTRG 40.4 40.4.1 Product Dependencies Power Management The ADC is automatically clocked after the first conversion in Normal Mode. In Sleep Mode, the ADC clock is automatically stopped after each conversion. As the logic is small and the ADC cell can be put into Sleep Mode, the Power Management Controller has no effect on the ADC behavior. Interrupt Sources The ADC interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the ADC interrupt requires the AIC to be programmed first. Analog Inputs The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding channel is enabled by writing the register ADC_CHER. By default, after reset, the PIO line is configured as input with its pull-up enabled and the ADC input is connected to the GND. 40.4.2 40.4.3 40.4.4 I/O Lines The pin ADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO Controller should be set accordingly to assign the pin ADTRG to the ADC function. 40.4.5 Timer Triggers Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the timer counters may be non-connected. 40.4.6 Conversion Performances For performance and electrical characteristics of the ADC, see the DC Characteristics section. 744 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 40.5 40.5.1 Functional Description Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the "ADC Mode Register" on page 752 and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to 63 (0x3F). PRESCAL must be programmed in order to provide an ADC clock frequency according to the parameters given in the Product definition section. 40.5.2 Conversion Reference The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages convert to values based on a linear conversion. Conversion Resolution The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit LOWRES in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By setting the bit LOWRES, the ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0. Moreover, when a PDC channel is connected to the ADC, 10-bit resolution sets the transfer request sizes to 16-bit. Setting the bit LOWRES automatically switches to 8-bit data transfers. In this case, the destination buffers are optimized. 40.5.3 745 6384D-ATARM-04-May-09 40.5.4 Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt. Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit and the EOC bit corresponding to the last converted channel. Figure 40-2. EOCx and DRDY Flag Behavior Write the ADC_CR with START = 1 Read the ADC_CDRx Write the ADC_CR with START = 1 Read the ADC_LCDR CHx (ADC_CHSR) EOCx (ADC_SR) Conversion Time Conversion Time DRDY (ADC_SR) 746 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE) flag is set in the Status Register (ADC_SR). In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in ADC_SR. The OVRE and GOVRE flags are automatically cleared when ADC_SR is read. Figure 40-3. GOVRE and OVREx Flag Behavior Read ADC_SR ADTRG CH0 (ADC_CHSR) CH1 (ADC_CHSR) ADC_LCDR ADC_CDR0 ADC_CDR1 Undefined Data Undefined Data Undefined Data Data A Data A Data B Data C Data C Data B EOC0 (ADC_SR) Conversion Conversion Read ADC_CDR0 EOC1 (ADC_SR) Conversion Read ADC_CDR1 GOVRE (ADC_SR) DRDY (ADC_SR) OVRE0 (ADC_SR) Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable. 747 6384D-ATARM-04-May-09 40.5.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the bit START at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the field TRGSEL in the Mode Register (ADC_MR). The selected hardware trigger is enabled with the bit TRGEN in the Mode Register (ADC_MR). If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform Mode. Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Registers enable the analog channels to be enabled or disabled independently. If the ADC is used with a PDC, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger. 40.5.6 Sleep Mode and Conversion Sequencer The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep Mode is selected by setting the bit SLEEP in the Mode Register ADC_MR. The SLEEP mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption. When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account. The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using a Timer/Counter output. The periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the PDC. Note: The reference voltage pins always remain connected in normal mode as in sleep mode. 748 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 40.5.7 ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register ADC_MR. In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be programmed through the bitfield SHTIM in the Mode Register ADC_MR. Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to program a precise value in the SHTIM field. See the section, ADC Characteristics in the product datasheet. 749 6384D-ATARM-04-May-09 40.6 Analog-to-Digital Converter (ADC) User Interface Register Mapping Register Control Register Mode Register Reserved Reserved Channel Enable Register Channel Disable Register Channel Status Register Status Register Last Converted Data Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Data Register 0 Channel Data Register 1 ... Channel Data Register 3 Reserved Name ADC_CR ADC_MR - - ADC_CHER ADC_CHDR ADC_CHSR ADC_SR ADC_LCDR ADC_IER ADC_IDR ADC_IMR ADC_CDR0 ADC_CDR1 ... ADC_CDR3 - Access Write-only Read-write - - Write-only Write-only Read-only Read-only Read-only Write-only Write-only Read-only Read-only Read-only ... Read-only - Reset - 0x00000000 - - - - 0x00000000 0x000C0000 0x00000000 - - 0x00000000 0x00000000 0x00000000 ... 0x00000000 - Table 40-2. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 ... 0x3C 0x44 - 0xFC 750 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 40.6.1 Name: Access: 31 ADC Control Register ADC_CR Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - - - - - - START SWRST * SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. * START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion. 751 6384D-ATARM-04-May-09 40.6.2 Name: Access: 31 ADC Mode Register ADC_MR Read-write 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 19 18 SHTIM 17 16 - 15 - 14 - 13 12 11 STARTUP 10 9 8 - 7 - 6 5 4 3 PRESCAL 2 1 0 - - SLEEP LOWRES TRGSEL TRGEN * TRGEN: Trigger Enable TRGEN 0 1 Selected TRGEN Hardware triggers are disabled. Starting a conversion is only possible by software. Hardware trigger selected by TRGSEL field is enabled. * TRGSEL: Trigger Selection TRGSEL 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Selected TRGSEL TIOA Ouput of the Timer Counter Channel 0 TIOA Ouput of the Timer Counter Channel 1 TIOA Ouput of the Timer Counter Channel 2 Reserved Reserved Reserved External trigger Reserved * LOWRES: Resolution LOWRES 0 1 Selected Resolution 10-bit resolution 8-bit resolution * SLEEP: Sleep Mode SLEEP 0 1 Selected Mode Normal Mode Sleep Mode 752 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary * PRESCAL: Prescaler Rate Selection ADCClock = MCK / ( (PRESCAL+1) * 2 ) * STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCClock * SHTIM: Sample & Hold Time Sample & Hold Time = (SHTIM+1) / ADCClock 753 6384D-ATARM-04-May-09 40.6.3 Name: Access: 31 ADC Channel Enable Register ADC_CHER Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - - - - CH3 CH2 CH1 CH0 * CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel. 754 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 40.6.4 Name: Access: 31 ADC Channel Disable Register ADC_CHDR Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - - - - CH3 CH2 CH1 CH0 * CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel. Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable. 755 6384D-ATARM-04-May-09 40.6.5 Name: Access: 31 ADC Channel Status Register ADC_CHSR Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - - - - CH3 CH2 CH1 CH0 * CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled. 756 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 40.6.6 Name: Access: 31 ADC Status Register ADC_SR Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 - 7 - 6 - 5 - 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 - - - - EOC3 EOC2 EOC1 EOC0 * EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished. 1 = Corresponding analog channel is enabled and conversion is complete. * OVREx: Overrun Error x 0 = No overrun error on the corresponding channel since the last read of ADC_SR. 1 = There has been an overrun error on the corresponding channel since the last read of ADC_SR. * DRDY: Data Ready 0 = No data has been converted since the last read of ADC_LCDR. 1 = At least one data has been converted and is available in ADC_LCDR. * GOVRE: General Overrun Error 0 = No General Overrun Error occurred since the last read of ADC_SR. 1 = At least one General Overrun Error has occurred since the last read of ADC_SR. * ENDRX: End of RX Buffer 0 = The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR. * RXBUFF: RX Buffer Full 0 = ADC_RCR or ADC_RNCR have a value other than 0. 1 = Both ADC_RCR and ADC_RNCR have a value of 0. 757 6384D-ATARM-04-May-09 40.6.7 Name: Access: 31 ADC Last Converted Data Register ADC_LCDR Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 1 LDATA 0 LDATA * LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. 758 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 40.6.8 Name: Access: 31 ADC Interrupt Enable Register ADC_IER Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 - 7 - 6 - 5 - 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 - - - - EOC3 EOC2 EOC1 EOC0 * EOCx: End of Conversion Interrupt Enable x * OVREx: Overrun Error Interrupt Enable x * DRDY: Data Ready Interrupt Enable * GOVRE: General Overrun Error Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 759 6384D-ATARM-04-May-09 40.6.9 Name: Access: 31 ADC Interrupt Disable Register ADC_IDR Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 - 7 - 6 - 5 - 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 - - - - EOC3 EOC2 EOC1 EOC0 * EOCx: End of Conversion Interrupt Disable x * OVREx: Overrun Error Interrupt Disable x * DRDY: Data Ready Interrupt Disable * GOVRE: General Overrun Error Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 760 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 40.6.10 Name: Access: 31 ADC Interrupt Mask Register ADC_IMR Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 - 7 - 6 - 5 - 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 - - - - EOC3 EOC2 EOC1 EOC0 * EOCx: End of Conversion Interrupt Mask x * OVREx: Overrun Error Interrupt Mask x * DRDY: Data Ready Interrupt Mask * GOVRE: General Overrun Error Interrupt Mask * ENDRX: End of Receive Buffer Interrupt Mask * RXBUFF: Receive Buffer Full Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 761 6384D-ATARM-04-May-09 40.6.11 Name: Access: 31 ADC Channel Data Register ADC_CDRx Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 1 DATA 0 DATA * DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled. 762 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 41. AT91SAM9G20 Electrical Characteristics 41.1 Absolute Maximum Ratings Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 41-1. Operating Temperature (Industrial)............-40 C to + 85 C Junction Temperature ............................................... +125C Storage Temperature ................................. -40C to + 150C Voltage on Input Pins with Respect to Ground .... -0.3V to VDDIO+0.3V (+4V max) Maximum Operating Voltage (VDDCORE, VDDPLL and VDDBU).............................. 1.2V Maximum Operating Voltage (VDDIOM and VDDIOP) ................................................ 4.0V Total DC Output Current on all I/O lines ................... 350 mA 763 6384D-ATARM-04-May-09 41.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40C to 85C, unless otherwise specified. Table 41-2. Symbol VVDDCORE VVDDBU VVDDPLL VVDDOSC VVDDIOM VVDDIOP VVDDANA VVDDUSB VIL VIH DC Characteristics Parameter DC Supply Core DC Supply Backup DC Supply PLL DC Supply Oscillator DC Supply Memory I/Os DC Supply Peripheral I/Os DC Supply Analog DC Supply USB Input Low-level Voltage VVDDIO from 3.0V to 3.6V VVDDIO from 1.65V to 1.95V VVDDIO from 3.0V to 3.6V VVDDIO from 1.65V to 1.95V IO Max, VVDDIO from 3.0V to 3.6V CMOS (IO <0.3 mA) VVDDIO from 1.65V to 1.95V TTL (IO Max) VVDDIO from 1.65V to 1.95V IO Max, VVDDIO from 3.0V to 3.6V VVDDIO - 0.4 VVDDIO - 0.1 VVDDIO - 0.4 40 240 140 75 190 1000 450 8 2 4 4 mA 18 mA kOhm selectable by software Conditions Min 0.9 0.9 0.9 1.65 1.65/3.0 1.65 3.0 3.0 -0.3 -0.3 2 0.7 x VVDDIO 3.3 3.3 1.8/3.3 Typ 1.0 1.0 1.0 Max 1.1 1.1 1.1 3.6 1.95/3.6 3.6 3.6 3.6 0.8 0.3 x VVDDIO VVDDIO + 0.3 VVDDIO + 0.3 0.4 0.1 0.4 Units V V V V V V V V V V V V V V V V V V Input High-level Voltage VOL Output Low-level Voltage VOH Output High-level Voltage CMOS (IO <0.3 mA) VVDDIO from 1.65V to 1.95V TTL (IO Max) VVDDIO from 1.65V to 1.95V PA0-PA31, PB0-PB31, PC0-PC3, NTRST and NRST RPULLUP Pull-up Resistance PC4 - PC31 VVDDIOM in 1.8V range PC4 - PC31 VVDDIOM in 3.3V range PA0-PA31 PB0-PB31 PC0-PC3 IO Output Current PC4 - PC31 in 3.3V range PC4 - PC31 in 1.8V range On VVDDCORE = 1.0V, T = 25C MCK = 0 Hz, excluding POR A All inputs driven TMS, TDI, TCK, NRST = 1 On VVDDBU = 1.0V, Logic cells consumption, excluding POR All inputs driven WKUP = 0 TA = 85C ISC Static Current TA = 25C TA = 85C 9 18 A 764 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 41.3 Power Consumption * Typical power consumption of PLLs, Slow Clock and Main Oscillator. * Power consumption of power supply in four different modes: Active, Idle, Ultra Low-power and Backup. * Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 41.3.1 Power Consumption versus Modes The values in Table 41-3 and Table 41-4 on page 766 are estimated values of the power consumption with operating conditions as follows: * VDDIOM = VDDIOP = 3.3V * VDDPLL = 1.0V * VDDCORE = VDDBU = 1.0V * TA = 25 C * There is no consumption on the I/Os of the device Figure 41-1. Measures Schematics VDDBU AMP1 VDDCORE AMP2 These figures represent the power consumption estimated on the power supplies. Table 41-3. Mode Power Consumption for Different Modes Conditions ARM Core clock is 400 MHz. MCK is 133 MHz. All peripheral clocks de-activated. onto AMP2 Idle state, waiting an interrupt. All peripheral clocks de-activated. onto AMP2 ARM Core clock is 500 Hz. All peripheral clocks de-activated. onto AMP2 Device only VDDBU powered onto AMP1 Consumption Unit Active 50 mA Idle 20 mA Ultra low power 8 mA Backup 9 A 765 6384D-ATARM-04-May-09 Table 41-4. Peripheral PIO Controller USART UHP UDP ADC TWI SPI MCI SSC Power Consumption by Peripheral in Active Mode Consumption 2.5 7.0 5.4 4.9 4.1 4.6 A/MHz 4.0 6.4 7.0 1.8 4.6 34.6 Unit Timer Counter Channels ISI EMAC 766 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 41.4 41.4.1 Clock Characteristics Processor Clock Characteristics Processor Clock Waveform Parameters Parameter Processor Clock Frequency Conditions VVDDCORE = 0.9V T = 85C Min Max 400 Units MHz Table 41-5. Symbol 1/(tCPPCK) 41.4.2 Master Clock Characteristics Master Clock Waveform Parameters Symbol 1/(tCPMCK) Note: Parameter Master Clock Frequency Conditions VVDDCORE = 0.9V T = 85C Min Max 133 Units MHz 1. The system clock is the maximum clock at which the system is able to run. It is given by the smallest value the of processor clock, internal bus clock, EBI clock. 41.4.3 XIN Clock Characteristics XIN Clock Electrical Characteristics Parameter XIN Clock Frequency XIN Clock Period XIN Clock High Half-period XIN Clock Low Half-period XIN Input Capacitance XIN Pull-down Resistor XIN Voltage (1) (1) (1) Table 41-6. Symbol 1/(tCPXIN) tCPXIN tCHXIN tCLXIN CIN RIN VIN Notes: Conditions Min Max 50 Units MHz ns 20 0.4 x tCPXIN 0.4 x tCPXIN 0.6 x tCPXIN 0.6 x tCPXIN 25 1000 3.3 ns ns pF k V 1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e. when MOSCEN = 0 and OSCBYPASS = 1) in the CKGR_MOR register. See "PMC Clock Generator Main Oscillator Register" in the PMC section. 767 6384D-ATARM-04-May-09 41.4.4 I/O Slew Rates The IOSR and VDDIOMSEL bits in the EBI_CSA register allow the user to program the rising and falling times of SDRAM signals. Rising/Falling time is given between 30% and 70%. Table 41-7. VDDIOMSEL 0 0 1 1 SDRAM Clock IOSR 0 1 0 1 Conditions 1.8V range, FAST slew rate, CLOAD = 10 pF 1.8V range, SLOW slew rate, CLOAD = 10 pF 3.3V range, FAST slew rate, CLOAD = 10 pF 3.3V range, SLOW slew rate, CLOAD = 10 pF Rising time (ns) 0.8 1.6 0.8 1.5 Falling time (ns) 1.0 1.5 0.8 1.6 Table 41-8. VDDIOMSEL 0 0 1 1 SDRAM Data, Address and Control IOSR 0 1 0 1 Conditions 1.8V range, FAST slew rate, CLOAD = 30 pF 1.8V range, SLOW slew rate, CLOAD = 30 pF 3.3V range, FAST slew rate, CLOAD = 50 pF 3.3V range, SLOW slew rate, CLOAD = 50 pF Rising time (ns) 1.5 1.7 2.8 6.0 Falling time (ns) 1.5 1.8 3.1 5.7 768 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 41.5 Crystal Oscillator Characteristics The following characteristics are applicable to the operating temperature range: TA = -40C to 85C and worst case of power supply, unless otherwise specified. 41.5.1 32 kHz Oscillator Characteristics 32 kHz Oscillator Characteristics Parameter Crystal Oscillator Frequency Load Capacitance External Load Capacitance Duty Cycle VDDBU = 1.0V, RS = 50 k(1) tST Startup Time VDDBU = 1.0V RS = 100 k(1) Notes: 1. RS is the equivalent series resistance. 2. CLEXT32 is determined by taking into account internal, parasitic and package load capacitance. AT91SAM92G20 Table 41-9. Symbol 1/(tCP32KHz) CCRYSTAL32 CLEXT32(2) Conditions Min Typ 32 768 Max Unit kHz Crystal @ 32.768 kHz CCRYSTAL32 = 6 pF CCRYSTAL32 = 12.5 pF 6 6 19 40 CCRYSTAL32 = 6 pF CCRYSTAL32 = 12.5 pF CCRYSTAL32 = 6 pF CCRYSTAL32 = 12.5 pF 12.5 pF pF pF 60 300 900 600 1200 % ms ms ms ms XIN32 XOUT32 GNDBU CCRYSTAL32 CLEXT32 CLEXT32 41.5.2 32 kHz Crystal Characteristics Table 41-10. 32 kHz Crystal Characteristics Symbol ESR CM CS Parameter Equivalent Series Resistor Rs Motional Capacitance Shunt Capacitance Conditions Crystal @ 32.768 kHz Crystal @ 32.768 kHz Crystal @ 32.768 kHz Min Typ 50 Max 100 3 2 Unit k pF pF 769 6384D-ATARM-04-May-09 41.5.3 RC Oscillator Characteristics Table 41-11. RC Oscillator Characteristics Symbol 1/(tCPRCz) Parameter Crystal Oscillator Frequency Duty Cycle tST Startup Time Conditions Min 20 45 Typ 32 Max 44 55 75 Unit kHz % s 41.5.4 Slow Clock Selection Table 41-12 defines the states for OSCSEL signal. Table 41-12. Slow Clock Selection OSCSEL 0 1 Slow Clock Internal RC External 32768Hz Startup Time (Max) 150 s 1200 ms The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. The 32,768 Hz startup delay is 1200 ms whereas it is 150 s for the internal RC oscillator (refer to Table 41-12). The pin OSCSEL must be tied either to GND or VDDBU for correct operation of the device. 770 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 41.5.5 Main Oscillator Characteristics Table 41-13. Main Oscillator Characteristics Symbol 1/(tCPMAIN) CCRYSTAL CLEXT(7) Parameter Crystal Oscillator Frequency Crystal Load Capacitance External Load Capacitance Duty Cycle VDDOSC = 3 to 3.6V CS = 3 pF(1) 1/(tCPMAIN) = 3 MHz CS = 7 pF(1) 1/(tCPMAIN) = 8 MHz CS = 7 pF(1) 1/(tCPMAIN) = 16 MHz CS = 7 pF(1) 1/(tCPMAIN) = 20 MHz Standby mode @ 3 MHz @ 8 MHz PON Drive Level @ 16 MHz @ 20 MHz @ 3 MHz @ 8 MHz IDD ON Current Dissipation (2) (3) Conditions Min 3 12.5 Typ 16 Max 20 17.5 Unit MHz pF pF pF CCRYSTAL = 12.5 pF(6) CCRYSTAL = 17.5 pF (6) 16 26 40 50 60 14.5 4 1.4 1 1 15 30 % tST Startup Time ms IDDST Standby Current Consumption A W 50 50 280 380 500 580 380 510 A 630 750 @ 16 MHz(4) @ 20 MHz(5) Notes: 1. CS is the shunt capacitance. 2. RS = 100 to 200 ; CS = 2.0 to 2.5 pF; CM = 2 to 1.5 pF (typ, worst case) using 1 k serial resistor on XOUT. 3. RS = 50 to 100 ; CS = 2.0 to 2.5 pF; CM = 4 to 3 pF (typ, worst case). 4. RS = 25 to 50 ; CS = 2.5 to 3.0 pF; CM = 7 to 5 pF (typ, worst case). 5. RS = 20 to 50 ; CS = 3.2 to 4.0 pF; CM = 10 to 8 pF (typ, worst case). 6. Additional user load capacitance should be subtracted from CLEXT. 7. CLEXT is determined by taking into account internal, parasitic and package load capacitance. AT91SAM92G20 XIN XOUT GNDPLL 1K CCRYSTAL CLEXT CLEXT 771 6384D-ATARM-04-May-09 41.5.6 Crystal Characteristics Table 41-14. Crystal Characteristics Symbol Parameter Conditions Fundamental @ 3 MHz Fundamental @ 8 MHz ESR Equivalent Series Resistor Rs Fundamental @ 16 MHz Fundamental @ 20 MHz CM CS Motional Capacitance Shunt Capacitance 80 50 8 7 pF pF Min Typ Max 200 100 Unit 41.5.7 PLL Characteristics Table 41-15. PLLA Characteristics Symbol FOUT FIN IPLL Parameter Output Frequency Input Frequency active mode Current Consumption standby mode 1 A Conditions Refer to following table Min 400 2 3.6 Typ Max 800 32 8 Unit MHz MHz mA Following configuration of ICPLLA and OUTA must be done for each PLLA frequency range. Table 41-16. PLLA Frequency Regarding ICPLLA and OUTA PLL Frequency Range (MHz) 745 - 800 695 - 750 645 - 700 595 - 650 545 - 600 495 - 550 445 - 500 400 - 450 ICPLLA 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 OUTA 0 1 0 1 0 1 0 1 . Table 41-17. PLLB Characteristics Symbol FOUT FIN IPLL Parameter Output Frequency Input Frequency Active mode @100 MHz Current Consumption Standby mode 1 A Conditions Field OUT of CKGR_PLL is 00 Min 30 2 Typ Max 100 32 1.2 Unit MHz MHz mA 772 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 41.6 ADC Table 41-18. ADC Characteristics 9-bit Mode Code R INL DNL OS GE fCLK Parameter Resolution Integral Non-linearity Differential Non-linearity Offset Error Gain Error Clock Frequency Converion Rate: Conversion Time Track-and-Hold Acquistion Time Throughput Rate Clock Frequency = 5 MHz see Note (1) Condition & Notes Min Typ 9 Max Unit Bits 2 No missing code Not including VREFN error -1.5 No missing code -1 +2 3 3.5 5 LSB LSB LSB LSB MHz 2 500 330 s ns KSPS @ fCLK = 5 MHz with TTH = 1 s Table 41-19. ADC Characteristics 10-bit Mode Code R INL DNL OS GE fCLK Parameter Resolution Integral Non-linearity Differential Non-linearity Offset Error Gain Error Clock Frequency Converion Rate: Conversion Time Track-and-Hold Acquistion Time Throughput Rate Note: Clock Frequency = 5 MHz see Note (1) Condition & Notes Min Typ 10 Max Unit Bits 2 No missing code Not including VREFN error -1.5 No missing code -1 1 3 3.5 1 LSB LSB LSB LSB MHz 10 500 95 s ns KSPS @ fCLK = 5 MHz with TTH = 1 s 1. In worst case, the Track-and-Hold Acquisition Time is given by: TTH (s) = 1.2 + ( 0.09 x Z IN ) ( kOhm ) In case of very high input impedance, this value must be respected in order to guarantee the correct converted value. An internal input current buffer supplies the current required for the low input impedance (1 mA max). 773 6384D-ATARM-04-May-09 To achieve optimal performance of the ADC, the analog power supply VDDANA and the ADVREF input voltage must be decoupled with a 4.7F capacitor in parallel with a 100 nF capacitor. Table 41-20. External Voltage Reference Input Parameter ADVREF Input Voltage Range ADVREF Average Current Current Consumption on VDDANA 300 Conditions Min 2.4 Typ Max VDDANA 220 620 Units V A A Table 41-21. Analog Inputs Parameter Input Voltage Range Input Leakage Current Input Capacitance 8 Min 0 Typ Max ADVREF 1 Units V A pF 774 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 41.7 41.7.1 USB Transceiver Characteristics Electrical Characteristics Table 41-22. Electrical Parameters Symbol Input Levels VIL VIH VDI VCM CIN I REXT Output Levels VOL VOH VCRS Low Level Output High Level Output Output Signal Crossover Voltage Measured with RL of 1.425 k tied to 3.6V Measured with RL of 14.25 k tied to GND Measure conditions described in Figure 41-23 0.0 2.8 1.3 0.3 3.6 2.0 V V V Low Level High Level Differential Input Sensitivity Differential Input Common Mode Range Transceiver capacitance Hi-Z State Data Line Leakage Recommended External USB Series Resistor Capacitance to ground on each line 0V < VIN < 3.3V In series with each USB pin with 5% - 10 27 |(D+) - (D-)| 2.0 0.2 0.8 2.5 9.18 + 10 0.8 V V V V pF A Parameter Conditions Min Typ Max Unit Pull-up and Pull-down Resistor RPUI Bus Pull-up Resistor on Upstream Port (idle bus) Bus Pull-up Resistor on Upstream Port (upstream port receiving) Bus Pull-down resistor 0.900 1.575 kOhm RPUA RPD 1.425 14.25 3.090 24.8 kOhm kOhm 775 6384D-ATARM-04-May-09 41.8 Core Power Supply POR Characteristics Table 41-23. Power-On-Reset Characteristics Symbol Vth+ VthTRES Parameter Threshold Voltage Rising Threshold Voltage Falling Reset Time Conditions Minimum Slope of +1.0V/100ms Min 0.5 0.4 30 Typ 0.7 0.6 70 Max 0.89 0.85 130 Units V V s 41.8.1 Power Sequence Requirements The AT91SAM9G20 board design must comply with the power-up and power-down sequence guidelines below to guarantee reliable operation of the device. Any deviation from these sequences may lead to the following situations: * Excessive current consumption during the power-up phase which, in the worst case, can result in irreversible damage to the device. * Prevent the device from booting. 41.8.2 Power-up Sequence The power sequence described below is applicable to all the AT91SAM9G20 revisions. However, the power sequence can be simplified for the revision B device. In this revision, the over consumption during the power-up phase has been limited to less than 200 mA. This current can not damage the device and if it is acceptable for the final application, the power sequence becomes VDDIO followed by VDDCORE. VDDIO must be established first to ensure a correct sampling of the BMS signal and also to guaranty the correct voltage level when accessing an external memory. Figure 41-2. VDDCORE and VDDIO Constraints at Startup VDD (V) VDDIOtyp Voh (2.6V) VDDIO VDDIO > Voh VDDCOREtyp 0.7V Vth+ (0.5V) VDDCORE t <--------------------- T1---------------------> Core Supply POR output SLCK 776 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Shown below is an example of the implementation on the AT91SAM9G20-EK Rev.C. 10 SQUARE CM COPPER AREA FOR HEAT SINKING WITH NO SOLDER MASK MN1 LT1963AEQ-3.3 R168 NOT POPULATED REGULATED 5V ONLY J1 5V R3 100K 1 2 + C1 330F C2 10F 10V 2 6 GND 3V3 CURRENT MEASURE J2 IRLML6402 3V3 Q3 3 VIN SD VOUT GND 3 FB 5 4 2 3 CR1 5V 1 C3 10F C4 10F R163 10K R161 82K 5V 1 R164 1K 8 5+ 6Q2 6 Si1563EDH MN15B 7 LM293 5V 5 4 R162 15K 4 C147 100NF J3 FORCE POWER ON C14 15PF 1 2 R9 10K 3 R10 10K R169 NOT POPULATED C5 1F C6 1F SHDN 8 5V 5V 5V 6 3 4 C2P VOUT 7 C11 R7 22F 30K 1V0 C1M 5 VIN C1P C2M C12 10PF R167 10K R165 15K C15 4.7F TPS60500 FB 1 EN MN3 10 2 R11 120K GND 9 PG R166 10K MMSD4148 VDDCORE and VDDBU are controlled by Power-on-Reset (POR) to gurantee that these power sources reach their target values prior to the release of POR. (See Figure 41-2.) * VDDIOM and VDDIOP must NOT be powered until VDDCORE has reached a level superior or equal to Vth+ (0.5V). * VDDIOM and VDDIOP must be 0.7V within (T2 + T3) after VDDCORE reaches Vth+ (0.5V). * VDDIOM and VDDIOP must reach Voh (2.6V) within (T2 +T3 +T4) after VDDCORE has reached Vth+ (0.5V). * T2 = Tres = 30 s * T3 = 3 x Tslck * T4 = 14 x Tslck 6384D-ATARM-04-May-09 + 3 - 2 MN15A 1 LM293 D1 777 Tsclk min (22 s) is obtained for the maximum frequency of the internal RC oscillator (44 kHz). This gives: * T2 = Tres = 30 s * T3 = 66 s * T4 = 308 s 41.8.3 Power-down Sequence Switch off the VDDIOM and VDDIOP power supplies prior to, or at the same time, as VDDCORE. No power-up or power-down restrictions apply to VDDBU, VDDPL, VDDANA and VDDUSB. 778 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 41.9 EBI Timings SMC Timings are given in MAX (T = 85C, VDDCORE = 0.9V) corner. Timings are given assuming a capacitance load on data, control and address pads: Table 41-24. Capacitance Load Corner IO Supply 3.3V 1.8V MAX 50 pF 30 pF In the following tables tCPMCK is MCK period. 41.9.1 Read Timings Table 41-25. SMC Read Signals - NRD Controlled (READ_MODE= 1) Symbol Parameter VDDIOM Supply 1.8V NO HOLD SETTINGS (nrd hold = 0) SMC1 SMC2 Data Setup before NRD High Data Hold after NRD High 13.0 0 11.4 0 ns ns Min 3.3V Units HOLD SETTINGS (nrd hold ...0) SMC3 SMC4 Data Setup before NRD High Data Hold after NRD High 9.6 0 8.0 0 ns ns HOLD or NO HOLD SETTINGS (nrd hold ...0, nrd hold =0) SMC5 NBS0/A0, NBS1, NBS2/A1, NBS3, A2 - A25 Valid before NRD High (nrd setup + nrd pulse)* tCPMCK 0.4 (nrd setup + nrd pulse - ncs rd setup) * tCPMCK + 0.5 nrd pulse * tCPMCK + 0.2 (nrd setup + nrd pulse)* tCPMCK 0.4 (nrd setup + nrd pulse - ncs rd setup) * tCPMCK + 0.4 nrd pulse * tCPMCK + 0.1 ns SMC6 NCS low before NRD High ns SMC7 NRD Pulse Width ns Table 41-26. SMC Read Signals - NCS Controlled (READ_MODE= 0) Symbol Parameter VDDIOM supply 1.8V NO HOLD SETTINGS (ncs rd hold = 0) SMC8 SMC9 Data Setup before NCS High Data Hold after NCS High 12.6 0 11.0 0 ns ns Min 3.3V Units 779 6384D-ATARM-04-May-09 Table 41-26. SMC Read Signals - NCS Controlled (READ_MODE= 0) (Continued) HOLD SETTINGS (ncs rd hold ...0) SMC10 SMC11 Data Setup before NCS High Data Hold after NCS High 9.2 0 7.6 0 ns ns HOLD or NO HOLD SETTINGS (ncs rd hold ...0, ncs rd hold = 0) SMC12 NBS0/A0, NBS1, NBS2/A1, NBS3, A2 - A25 valid before NCS High (ncs rd setup + ncs rd pulse)* tCPMCK -0.8 (ncs rd setup + ncs rd pulse nrd setup)* tCPMCK -0.2 ncs rd pulse length * tCPMCK + 0.1 (ncs rd setup + ncs rd pulse)* tCPMCK -0.6 (ncs rd setup + ncs rd pulse nrd setup)* tCPMCK -0.3 ncs rd pulse length * tCPMCK 0.1 ns SMC13 NRD low before NCS High ns SMC14 NCS Pulse Width ns 41.9.2 Write Timings Table 41-27. SMC Write Signals - NWE controlled (WRITE_MODE = 1) Min Symbol Parameter 1.8V Supply 3.3V Supply Units HOLD or NO HOLD SETTINGS (nwe hold ...0, nwe hold = 0) SMC15 SMC16 SMC17 Data Out Valid before NWE High NWE Pulse Width NBS0/A0 NBS1, NBS2/A1, NBS3, A2 - A25 valid before NWE low nwe pulse * tCPMCK -0.8 nwe pulse * tCPMCK -0.4 nwe setup * tCPMCK -0.5 (nwe setup - ncs rd setup + nwe pulse) * tCPMCK 0.2 nwe pulse * tCPMCK -0.8 nwe pulse * tCPMCK -0.4 nwe setup * tCPMCK -0.5 (nwe setup - ncs rd setup + nwe pulse) * tCPMCK 0.2 ns ns ns SMC18 NCS low before NWE high ns HOLD SETTINGS (nwe hold ...0) SMC19 NWE High to Data OUT, NBS0/A0 NBS1, NBS2/A1, NBS3, A2 - A25 change NWE High to NCS Inactive (1) nwe hold * tCPMCK -0.4 (nwe hold - ncs wr hold)* tCPMCK 0.3 nwe hold * tCPMCK -0.4 (nwe hold - ncs wr hold)* tCPMCK -0.3 ns SMC20 ns NO HOLD SETTINGS (nwe hold = 0) SMC21 NWE High to Data OUT, NBS0/A0 NBS1, NBS2/A1, NBS3, A2 - A25, NCS change(1) 3.4 3.1 ns Note: 1. hold length = total cycle duration - setup duration - pulse duration. "hold length" is for "ncs wr hold length" or "NWE hold length". 780 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 41-28. SMC Write NCS Controlled (WRITE_MODE = 0) Min Symbol SMC22 SMC23 SMC24 Parameter Data Out Valid before NCS High NCS Pulse Width NBS0/A0 NBS1, NBS2/A1, NBS3, A2 - A25 valid before NCS low 1.8V Supply ncs wr pulse * tCPMCK -0.8 ncs wr pulse * tCPMCK + 0.1 ncs wr setup * tCPMCK -0.6 (ncs wr setup nwe setup + ncs pulse)* tCPMCK 0.4 ncs wr hold * tCPMCK -0.2 (ncs wr hold nwe hold)* tCPMCK -0.2 3.3V Supply ncs wr pulse * tCPMCK -0.7 ncs wr pulse * tCPMCK -0.1 ncs wr setup * tCPMCK -0.6 (ncs wr setup nwe setup + ncs pulse)* tCPMCK 0.3 ncs wr hold * tCPMCK -0.2 (ncs wr hold nwe hold)* tCPMCK -0.2 Units ns ns ns SMC25 NWE low before NCS high ns SMC26 NCS High to Data Out, NBS0/A0, NBS1, NBS2/A1, NBS3, A2 - A25, change NCS High to NWE Inactive ns SMC27 ns Figure 41-3. SMC Timings - NCS Controlled Read and Write SMC12 SMC12 SMC24 SMC26 A0/A1/NBS[3:0]/A2-A25 SMC13 SMC13 NRD NCS SMC14 SMC9 SMC14 SMC23 SMC8 SMC10 SMC11 SMC22 SMC26 D0 - D15 SMC25 SMC27 NWE NCS Controlled READ with NO HOLD NCS Controlled READ with HOLD NCS Controlled WRITE 781 6384D-ATARM-04-May-09 Figure 41-4. SMC Timings - NRD Controlled Read and NWE Controlled Write SMC5 SMC17 SMC21 SMC5 SMC17 SMC19 A0/A1/NBS[3:0]/A2-A25 SMC6 SMC18 SMC21 SMC6 SMC18 SMC20 NCS NRD SMC7 SMC7 SMC1 SMC2 SMC15 SMC21 SMC3 SMC4 SMC15 SMC19 D0 - D31 NWE SMC16 SMC16 NRD Controlled READ with NO HOLD NWE Controlled WRITE with NO HOLD NRD Controlled READ with HOLD NWE Controlled WRITE with HOLD 41.10 SDRAMC Timings Timings are given assuming a capacitance load on data, control and address pads : Table 41-29. Capacitance Load on data, control and address pads Corner IO Supply 3.3V 1.8V MAX 50pF 30 pF Table 41-30. Capacitance Load on SDCK pad Corner IO Supply 3.3V 1.8V MAX 10pF 10pF The SDRAM Controller satisfies the timings of standard PC100, PC133 (3.3V supply) and Mobile SDRAM (1.8 supply) that are given in Table 41-31, Table 41-32 and Table 41-33. Table 41-31. SDRAM PC100 Characteristics Min Parameter SDRAM Controller Clock Frequency Control/Address/Data In Setup Control/Address/Data In Hold (1)(2) Max 3.3V Supply 100 Units MHz ns ns 6 ns ns 3.3V Supply 2 1 (1)(2) Data Out Access time after SDCK rising Data Out change time after SDCK rising 3 782 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 41-32. SDRAM PC133 Characteristics Min Parameter SDRAM Controller Clock Frequency Control/Address/Data In Setup(1)(2) Control/Address/Data In Hold (1)(2) Max 3.3V Supply 133 Units MHz ns ns 5.4 ns ns 3.3V Supply 1.5 0.8 Data Out Access time after SDCK rising Data Out change time after SDCK rising 3.0 Table 41-33. Mobile Characteristics Min Parameter SDRAM Controller Clock Frequency Control/Address/Data In Setup(1)(2) Control/Address/Data In Hold (1)(2) Max 1.8V Supply 133/100 (3) Units MHz ns ns 6.0 / 8.0 (3) 1.8V Supply 2.0 1.0 Data Out Access time after SDCK rising Data Out change time after SDCK rising Notes: 3.0 ns ns 1. Control is the set of following signals: SDCKE, SDCS, RAS, CAS, SDA10, BAx, DQMx, and SDWE. 2. Address is the set of A0-A9, A11-A13. 3. 133 MHz with CL = 3, 100 MHz with CL = 2. 783 6384D-ATARM-04-May-09 41.11 Peripheral Timings 41.11.1 EMAC Timings are given assuming a capacitance load on data and clock: Table 1. Capacitance Load on data, clock pads Corner IO Supply 3.3V 1.8V MAX 20pf 20pf The Ethernet controller satisfies the timings of standard in MAX corner. Table 41-34. EMAC Signals Relative to EMDC Symbol EMAC1 EMAC2 EMAC3 Parameter Setup for EMDIO from EMDC rising Hold for EMDIO from EMDC rising EMDIO toggling from EMDC rising Min (ns) 10 ns 10 ns 0 ns 300 ns Max (ns) 41.11.1.1 MII Mode Table 41-35. EMAC MII Specific Signals Symbol EMAC4 EMAC5 EMAC6 EMAC7 EMAC8 EMAC9 EMAC10 EMAC11 EMAC12 EMAC13 EMAC14 EMAC15 EMAC16 Note: Parameter Setup for ECOL from ETXCK rising Hold for ECOL from ETXCK rising Setup for ECRS from ETXCK rising Hold for ECRS from ETXCK rising ETXER toggling from ETXCK rising ETXEN toggling from ETXCK rising ETX toggling from ETXCK rising Setup for ERX from ERXCK Hold for ERX from ERXCK Setup for ERXER from ERXCK Hold for ERXER from ERXCK Setup for ERXDV from ERXCK Hold for ERXDV from ERXCK Min (ns) 10 10 10 10 10 10 10 10 10 10 10 10 10 25 25 25 Max (ns) 1. VDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF 784 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 41-5. EMAC MII Mode EMDC EMAC1 EMDIO EMAC4 ECOL EMAC6 ECRS EMAC7 EMAC5 EMAC2 EMAC3 ETXCK EMAC8 ETXER EMAC9 ETXEN EMAC10 ETX[3:0] ERXCK EMAC11 ERX[3:0] EMAC13 ERXER EMAC15 ERXDV EMAC16 EMAC14 EMAC12 Table 41-36. RMII Mode Symbol EMAC21 EMAC22 EMAC23 EMAC24 EMAC25 Parameter ETXEN toggling from EREFCK rising ETX toggling from EREFCK rising Setup for ERX from EREFCK rising Hold for ERX from EREFCK rising Setup for ERXER from EREFCK rising Min (ns) 2 2 4 2 4 Max (ns) 16 16 785 6384D-ATARM-04-May-09 Table 41-36. RMII Mode Symbol EMAC26 EMAC27 EMAC28 Parameter Hold for ERXER from EREFCK rising Setup for ECRSDV from EREFCK rising Hold for ECRSDV from EREFCK rising Min (ns) 2 4 2 Max (ns) Figure 41-6. EMAC RMII Timings EREFCK EMAC21 ETXEN EMAC22 ETX[1:0] EMAC23 ERX[1:0] EMAC25 ERXER EMAC27 ECRSDV EMAC28 EMAC26 EMAC24 41.11.2 SPI Timings are given assuming a capacitance load on MISO, SPCK and MOSI: Table 41-37. Capacitance Load for MISO, SPCK and MOSI Corner Supply 1.8V MAX 20 pF Figure 41-7. SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL =1 and NCPHA = 0) SPCK SPI0 MISO SPI1 SPI2 MOSI 786 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 41-8. SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL and NCPHA = 1) SPCK SPI3 MISO SPI4 SPI5 MOSI Figure 41-9. SPI Slave Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0) SPCK SPI6 MISO SPI7 MOSI SPI8 Figure 41-10. SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1) SPCK SPI9 MISO SPI10 MOSI SPI11 Note: 1. CLOAD is 8 pF for MISO and 6 pF for SPCK and MOSI. 787 6384D-ATARM-04-May-09 Figure 41-11. SPI Slave Mode - NPCS Timings SPI14 SPI6 SPCK (CPOL = 0) SPI12 SPCK (CPOL = 1) SPI16 MISO SPI9 SPI15 SPI13 Table 41-38. SPI Timings Symbol Parameter Conditions Master Mode SPI0 SPI1 SPI2 SPI3 SPI4 SPI5 MISO Setup time before SPCK rises MISO Hold time after SPCK rises SPCK rising to MOSI MISO Setup time before SPCK falls MISO Hold time after SPCK falls SPCK falling to MOSI MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range Min Max Units 14.5 + 0.5*tCPMCK -11.6 - 0.5* tCPMCK -0.6 14.7 + 0.5*tCPMCK -11.7 - 0.5* tCPMCK -0.7 ns ns ns ns ns ns Slave Mode SPI6 SPI7 SPI8 SPI9 SPI10 SPI11 SPI12 SPI13 SPI14 SPI15 SPI16 SPCK falling to MISO MOSI Setup time before SPCK rises MOSI Hold time after SPCK rises SPCK rising to MISO MOSI Setup time before SPCK falls MOSI Hold time after SPCK falls NPCS0 setup to SPCK rising NPCS0 hold after SPCK falling NPCS0 setup to SPCK falling NPCS0 hold after SPCK rising NPCS0 falling to MISO valid MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range MAX corner, VDDIOP in 1.8V range 14.7 5.8 -2.7 14.7 23.8 15.3 -8.3 10.9 -8.3 10.9 14.7 10.7 ns ns ns ns ns ns ns ns ns ns ns 788 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 41.11.3 SSC Timings are given assuming a capacitance load on clock and data signals. Table 41-39. Capacitance Load Corner Supply 3.3V 1.8V MAX 30pF 20pF Figure 41-12. SSC Transmitter, TK and TF in Output TK (CKI =1) TK (CKI =0) SSC0 TF/TD Figure 41-13. SSC Transmitter, TK in Input and TF in Output TK (CKI =1) TK (CKI =0) SSC1 TF/TD 789 6384D-ATARM-04-May-09 Figure 41-14. SSC Transmitter, TK in Output and TF in Input TK (CKI=1) TK (CKI=0) SSC2 TF SSC0 TD SSC3 Figure 41-15. SSC Transmitter, TK and TF in Input TK (CKI=1) TK (CKI=0) SSC4 TF SSC3 TD SSC5 Figure 41-16. SSC Receiver RK and RF in Input RK (CKI=0) RK (CKI=1) SSC6 RF/RD SSC7 790 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 41-17. SSC Receiver, RK in input and RF in Output RK (CKI=1) RK (CKI=0) SSC6 RD SSC8 RF SSC7 Figure 41-18. SSC Receiver, RK and RF in Output RK (CKI=1) RK (CKI=0) SSC9 RD SSC11 RF SSC10 Figure 41-19. SSC Receiver, RK in Output and RF in Input RK (CKI=0) RK (CKI=1) SSC9 RF/RD SSC10 791 6384D-ATARM-04-May-09 Table 41-40. SSC Timings Symbol Parameter Conditions Transmitter MAX corner, VDDIO = 1.8V Min Max Units SSC0 TK edge to TF/TD (TK output, TF output) MAX corner, VDDIO = 3.3V MAX corner, VDDIO = 1.8V -3.2 ((2) -2.7 -3.2 -2.7 (2) (2) (2) 4.2 (2) 3.7 4.2 3.7 (2) (2) (2) ns ns ns ns ns ns ns ns SSC1 TK edge to TF/TD (TK input, TF output) MAX corner, VDDIO = 3.3V MAX corner, VDDIO = 1.8V SSC2 TF setup time before TK edge (TK output) MAX corner, VDDIO = 3.3V MAX corner, VDDIO = 1.8V 21.2 - tCPMCK 15.5 - tCPMCK tCPMCK - 13.4 tCPMCK - 9.5 -3.1(1)(2) -2.6(1)(2) 7.4 - tCPMCK 6.0 - tCPMCK tCPMCK - 0.7 tCPMCK - 2.0 11.6(1) 7.7(1) 3 * tCPMCK + 17.0(1) 3 * tCPMCK + 11.3(1) 2 * tCPMCK + 4.3 (1)(2) 2 * tCPMCK + 3.8 (1)(2) SSC3 TF hold time after TK edge (TK output) MAX corner, VDDIO = 3.3V MAX corner, VDDIO = 1.8V ns ns ns ns ns ns ns ns SSC4 (1) TK edge to TF/TD (TK output, TF input) MAX corner, VDDIO = 3.3V MAX corner, VDDIO = 1.8V SSC5 TF setup time before TK edge (TK input) MAX corner, VDDIO = 3.3V MAX corner, VDDIO = 1.8V SSC6 TF hold time after TK edge (TK input) MAX corner, VDDIO = 3.3V MAX corner, VDDIO = 1.8V SSC7(1) TK edge to TF/TD (TK input, TF input) MAX corner, VDDIO = 3.3V Receiver MAX corner, VDDIO = 1.8V SSC8 RF/RD setup time before RK edge (RK input) MAX corner, VDDIO = 3.3V MAX corner, VDDIO = 1.8V 7.4 - tCPMCK 6.2 - tCPMCK tCPMCK +7.4 tCPMCK +6.1 11.3 7.3 (2) (2) (2) ns ns ns ns 22.3 16.5 ns ns ns ns ns ns ns ns SSC9 RF/RD hold time after RK edge (RK input) MAX corner, VDDIO = 3.3V MAX corner, VDDIO = 1.8V SSC10 RK edge to RF (RK input) MAX corner, VDDIO = 3.3V MAX corner, VDDIO = 1.8V (2) SSC11 RF/RD setup time before RK edge (RK output) MAX corner, VDDIO = 3.3V MAX corner, VDDIO = 1.8V 21.6 - tCPMCK 15.9 - tCPMCK tCPMCK - 10.5 tCPMCK - 6.5 -3.2 -2.8 (2) (2) SSC12 RF/RD hold time after RK edge (RK output) MAX corner, VDDIO = 3.3V MAX corner, VDDIO = 1.8V SSC13 Notes: RK edge to RF (RK output) MAX corner, VDDIO = 3.3V 1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or 7 (Receive Start Selection), two periods of the MCK must be added to timings. 2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or RK) edge and the signal change. The Max access timing is the time between the TK edge and the signal stabilization. Figure 41-20 illustrates Min and Max accesses for SSC0. The same appliess for SSC1, SSC4, and SSC7, SSC10 and SSC13. 792 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Figure 41-20. Min and Max Access for SSC0 TK (CKI =1) TK (CKI =0) SSC0min SSC0max TF/TD 41.11.4 ISI Timings are given assuming a capacitance load on clock and data signals. Table 41-41. Capacitance Load Corner Supply 3.3V 1.8V MAX 30pF 20pF Figure 41-21. ISI Timing Diagram PIXCLK 3 DATA[7:0] VSYNC HSYNC Valid Data Valid Data Valid Data 1 2 Table 41-42. ISI Timings with Peripheral Supply 3.3V Symbol ISI1 ISI2 ISI3 Parameter DATA/VSYNC/HSYNC setup time DATA/VSYNC/HSYNC hold time PIXCLK frequency Min 4.5 1.3 TBD Max Units ns ns MHz Table 41-43. ISI Timings with Peripheral Supply 1.8V Symbol ISI1 ISI2 ISI3 Parameter DATA/VSYNC/HSYNC setup time DATA/VSYNC/HSYNC hold time PIXCLK frequency Min 2.0 6.4 TBD Max Units ns ns MHz 793 6384D-ATARM-04-May-09 41.11.5 MCI Capacitance loads on data and clock are given in Table 41-44. Figure 41-22. MCI Timings MCI1 CLK MCI2 CMD_DAT Input MCI4 CMD_DAT Output Shaded areas are not valid MCI5 MCI3 Table 41-44. MCI Timings Symbol Parameter CLoad C = 25 pf MCI1 CLK frequency at Data transfer Mode C= 100 pf C= 250 pf CLK frequency at Identification Mode CLK Low time CLK High time CLK Rise time CLK Fall time CLK Low time CLK High time CLK Rise time CLK Fall time MCI2 MCI3 MCI4 MCI5 Input hold time Input setup time Output change after CLK rising Output valid before CLK rising C= 100 pf C= 100 pf C= 100 pf C= 100 pf C= 250 pf C= 250 pf C= 250 pf C= 250 pf 3 3 5 5 50 50 50 50 10 10 10 10 Min Max 25 20 20 400 Units MHz MHz MHz kHz ns ns ns ns ns ns ns ns ns ns ns ns 794 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 41.11.6 UDP Figure 41-23. USB Data Signal Rise and Fall Times Rise Time VCRS 10% Differential Data Lines tR (a) REXT=27 ohms Fosc = 6 MHz/750 kHz Buffer (b) Cload tF 90% 10% Fall Time Table 41-45. In Full Speed Symbol tFR tFE tFRFM Parameter Transition Rise Time Transition Fall Time Rise/Fall time Matching Conditions CLOAD = 50 pF CLOAD = 50 pF Min 4 4 90 Typ Max 20 20 111.11 Unit ns ns % 795 6384D-ATARM-04-May-09 42. AT91SAM9G20 Mechanical Characteristics 42.1 217-ball LFBGA Package Drawing Figure 42-1. 217-ball LFBGA Package Drawing Table 42-1. Ball Land Soldering Informations 0.43 mm +/- 0.05 0.30 mm +/- 0.05 Soldering Mask Opening Table 42-2. 450 Device and 217-ball LFBGA Package Maximum Weight mg Table 42-3. 217-ball LFBGA Package Characteristics 3 Moisture Sensitivity Level 796 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 42-4. Package Reference MO-205 e1 JEDEC Drawing Reference JESD97 Classification 42.1.1 Soldering Profile Table 42-5 gives the recommended soldering profile from J-STD-20. Table 42-5. Soldering Profile BGA217 green compliant Package 3 C/sec. max. 180 sec. max. 60 sec. to 150 sec. 20 sec. to 40 sec. 260 +0 C 6 C/sec. max. 8 min. max. BGA247 green compliant Package 3 C/sec. max. 180 sec. max. 60 sec. to 150 sec. 20 sec. to 40 sec. 260 +0 C 6 C/sec. max. 8 min. max. Profile Feature Average Ramp-up Rate (217C to Peak) Preheat Temperature 175C 25C Temperature Maintained Above 217C Time within 5 C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25 C to Peak Temperature Note: It is recommended to apply a soldering temperature higher than 250C A maximum of three reflow passes is allowed per component. 797 6384D-ATARM-04-May-09 42.2 247-ball TFBGA Package Drawing Figure 42-2. 247-ball TFBGA Drawing Table 42-6. Ball Pitch Ball Diameter Ball Information 0.50 mm 0.05 0.30 mm 0.05 798 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table 42-7. Ball Land Solder Mask Opening Soldering Information 0.35 mm 0.05 0.27 mm 0.05 Table 42-8. 177 Device and 247-ball TFBGA Package Maximum Weight mg Table 42-9. 247-ball TFBGA Package Characteristics 3 Moisture Sensitivity Level Table 42-10. Package Reference JEDEC Drawing Reference JESD97 Classification none e1 42.2.1 Soldering Profile Table 42-5 gives the recommended soldering profile from J-STD-20. Table 42-11. Soldering Profile Profile Feature Average Ramp-up Rate (217C to Peak) Preheat Temperature 175C 25C Temperature Maintained Above 217C Time within 5 C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25 C to Peak Temperature Note: Green Package 3 C/sec. max. 180 sec. max. 60 sec. to 150 sec. 20 sec. to 40 sec. 260 +0 C 6 C/sec. max. 8 min. max. It is recommended to apply a soldering temperature higher than 250C. A maximum of three reflow passes is allowed per component. 799 6384D-ATARM-04-May-09 43. AT91SAM9G20 Ordering Information Table 43-1. AT91SAM9G20 Ordering Information MRL B Ordering Code AT91SAM9G20B-CU AT91SAM9G20B-CFU Package BGA217 BGA247 Package Type Green Green Temperature Operating Range Industrial -40C to 85C Industrial -40C to 85C MRL A Ordering Code AT91SAM9G20-CU - 800 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 44. AT91SAM9G20 Errata 44.1 Marking All devices are marked with the Atmel logo and the ordering code. Additional marking has the following format: YYWW V XXXXXXXXX where * "YY": manufactory year * "WW": manufactory week * "V": revision ARM * "XXXXXXXXX": lot number 801 6384D-ATARM-04-May-09 44.2 AT91SAM9G20 Errata - Revision "A" Parts Refer to Section 44.1 "Marking" on page 801. 44.2.1 44.2.1.1 Analog-to-digital Converter (ADC) ADC: Sleep Mode If Sleep mode is activated while there is no activity (no conversion is being performed), it will take effect only after a conversion occurs. Problem Fix/Workaround To activate sleep mode as soon as possible, it is recommended to write successively, ADC Mode Register (SLEEP) then ADC Control Register (START bit field); to start an analog-to-digital conversion, in order put ADC into sleep mode at the end of this conversion. 44.2.2 44.2.2.1 Boot ROM Boot ROM: ROM Code, Internal RC Usage with SAM-BA Boot through USB Booting from the internal RC oscillator (OSCSEL = 0) prevents using SAM-BA Boot through the USB device interface. Problem Fix/Workaround Use SAM-BA Boot through DBGU (or AT91SAM-ICE JTAG-ICE interface with SAM-BA GUI) if the internal RC oscillator must be used. Boot from the 32 kHz external oscillator (OSCEL =1) to use SAM-BA Boot through the USB. 44.2.2.2 Boot ROM: MCCK Remains Active The ROM boot sequence is as follows; - DataFlash on SPI0 NPCS0 - DataFlash on SPI0 NPCS1 - NAND FLash - SDCard - TWI - SAM-BA Boot MCCK is not disabled after SDCard boot program. This does not affect the TWI boot program but must be considered by any applications using SAM-BA boot. Problem Fix/Workaround None. 44.2.3 44.2.3.1 Error Corrected Code Controller (ECC) ECC: 1-bit ECC per 512 Words 1-bit ECC per 512 words is not functional. Problem Fix/Workaround Perform the ECC computation by software. 802 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 44.2.4 44.2.4.1 MCI MCI: Busy Signal of R1b responses is not taken in account The busy status of the card during the response (R1b) is ignored for the commands CMD7, CMD28, CMD29, CMD38, CMD42, CMD56. Additionally, for commands CMD42 and CMD56 a conflict can occur on data line0 if the MCI sends data to the card while the card is still busy.The behavior is correct for CMD12 command (STOP_TRANSFER). Problem Fix/Workaround None. 44.2.4.2 MCI: SDIO Interrupt does not work with slots other than A If there is 1-bit data bus width on slots other than slot A, the SDIO interrupt can not be captured. The sample is made on the wrong data line. Problem Fix/Workaround None 44.2.4.3 MCI: Data Timeout Error Flag As the data Timeout error flag checking the Naac timing cannot rise, the MCI can be stalled waiting indefinitely the Data start bit. Problem Fix/Workaround A STOP command must be sent with a software timeout. 44.2.4.4 MCI: Data Write Operation and number of bytes The Data Write operation with a number of bytes less than 12 is impossible. Problem Fix/Workaround The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The BLKLEN or BCNT field are used to specify the real count number. 44.2.4.5 MCI: Flag Reset is not correct in half duplex mode In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be incorrect. These flags are reset correctly after a PDC channel enable. Problem Fix/Workaround Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the PDC channel by writing PDC_TXTEN or PDC_RXTEN. 803 6384D-ATARM-04-May-09 44.2.5 44.2.5.1 Reset Controller (RSTC) RSTC: Reset During SDRAM Accesses When a User Reset occurs during SDRAM read access, the SDRAM clock is turned off while data are ready to be read on the data bus. The SDRAM maintains the data until the clock restarts. If the user Reset is programmed to assert a general reset, the data maintained by the SDRAM leads to a data bus conflict and adversely affects the boot memories connected on the EBI: * NAND Flash boot functionality, if the system boots out of internal ROM. * NOR Flash boot, if the system boots on an external memory connected on the EBI CS0. Problem Fix/Workaround 1. Avoid User Reset to generate a system reset. 2. Trap the User Reset with an interrupt. In the interrupt routine, Power Down SDRAM properly and perform Peripheral and Processor Reset with software in assembler. Example with libV3. * The main code: //user reset interrupt setting // Configure AIC controller to handle SSC interrupts AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, sysc_handler ); // Enable SYSC interrupt in AIC AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS); *AT91C_RSTC_RMR = (0xA5<<24) | (0x4<<8) | AT91C_RSTC_URSTIEN; // AIC base address // System peripheral ID // Max priority AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED, // Level sensitive * The C SYS handler: extern void soft_user_reset(void); void sysc_handler(void){ //check if interrupt comes from RSTC if( (*AT91C_RSTC_RSR & AT91C_RSTC_URSTS ) == AT91C_RSTC_URSTS){ soft_user_reset(); //never reached while(1); } } * The assembler routine: 804 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary AREA TEST, CODE INCLUDEAT91SAM9xxx.inc EXPORTsoft_user_reset soft_user_reset ;disable IRQs MRS r0, CPSR ORR r0, r0, #0x80 MSR CPSR_c, r0 ;change refresh rate to block all data accesses LDR r0, =AT91C_SDRAMC_TR LDR r1, =1 STR r1, [r0] ;prepare power down command LDR r0, =AT91C_SDRAMC_LPR LDR r1, =2 ;prepare proc_reset and periph_reset LDR r2, =AT91C_RSTC_RCR LDR r3, =0xA5000005 ;perform power down command STR r1, [r0] ;perform proc_reset and periph_reset (in the ARM pipeline) STR r3, [r2] END 805 6384D-ATARM-04-May-09 44.2.6 44.2.6.1 Serial Peripheral Interface (SPI) SPI: Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0 If the SPI is used in the following configuration: * master mode * CPOL =1 and NCPHA = 0 * multiple chip selects used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock frequency equals the system clock frequency) and the other transfers set with SCBR not equal to 1 * transmit with the slowest chip select and then with the fastest one then an additional pulse will be generated on output PSCK during the second transfer. Problem Fix/Workaround Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and the others differ from 1 if CPHA = 0 and CPOL = 1. If all chip selects are configured with Baudrate = 1, the issue does not appear. 44.2.6.2 SPI: Baudrate set to 1 When Baudrate is set to 1 (i.e., when serial clock frequency equals the system clock frequency), and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15), an additional pulse is generated on output SPCK. No error occurs if BITS field equals 8,10,12,14 or 16 and Baudrate = 1. Problem Fix/Workaround None. 44.2.7 44.2.7.1 Serial Synchronous Controller (SSC) SSC: Unexpected RK clock cycle when RK outputs a clock during data transfer When the SSC receiver is used in the following configuration: * the internal clock divider is used (CKS =0 and DIV different from 0), * RK pin set as output and provides the clock during data transfer (CKO=2) * data sampled on RK falling edge (CKI =0) then, at the end of the data, the RK pin is set in high impedance which may be interpreted as an unexpected clock cycle. Problem Fix/Workaround Enable the pull-up on RK pin. 44.2.7.2 SSC: Incorrect first RK clock cycle when RK outputs a clock during data transfer When the SSC receiver is used in the following configuration: * RX clock is divided clock (CKS = 0 and DIV different from 0) * RK pin set as output and provides the clock during data transfer (CKO = 2) * data sampled on RK falling edge (CKI = 0) then the first clock cycle time generated by the RK pin is equal to MCK/(2 x (DIV +1)) instead of MCK/(2 x DIV). Problem Fix/Workaround 806 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary None. 44.2.7.3 SSC: Transmitter Limitations in Slave Mode If TK is programmed as output and TF is programmed as input, it is impossible to emit data when start of edge (rising or falling) of synchro with a Start Delay equal to zero. Problem Fix/Workaround None. 44.2.7.4 SSC: Periodic Transmission Limitations in Master Mode If Last Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent. Problem Fix/Workaround None. 44.2.8 44.2.8.1 Shutdown Controller (SHDWC) SHDWC: SHDN Signal may be Driven to Low Level Voltage During Device Power-on If only VDDBU is powered during boot sequence (No VDDCORE), the SHDN signal may be driven to low level voltage after a delay.This delay is linked to the startup time of the slow clock selected by OSCSEL signal. If SHDN pin is connected to the Enable pin (EN) of the VDDCORE regulator, VDDCORE establishment does not occur and the system does not start. Problem Fix/Workaround 1. VDDCORE must be established within the delay corresponding to the startup time of the slow clock selected by OSCSEL. 2. Add a glue logic to latch the rising edge of the SHDN signal. The reset of the latch output (EN_REG) can be connected to a PIO and used to enter the shutdown mode. 44.2.9 44.2.9.1 Static Memory Controller (SMC) SMC: Chip Select Parameters Modification The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if accesses are performed on this CS during the modification. For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code from a memory connected on this CS0, may lead to unpredictable behavior. Problem Fix/Workaround The code used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory connected to another Chip Select 44.2.10 44.2.10.1 System Controller (SYSC) SYSC: Possible Event Loss when reading RTT_SR If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when the RTT_SR is read, the corresponding bit might be cleared. This can lead to the loss of this event. Problem Fix/Workaround The software must handle an RTT event as an interrupt and should not poll RTT_SR. 807 6384D-ATARM-04-May-09 44.2.11 44.2.11.1 Two-wire Interface (TWI) TWI: RXRDY Flag is not reset by a SOFTWARE Reset The RXRDY Flag is not reset when a Software reset is performed. Problem Fix/Workaround After a Software Reset, the Register TWI_RHR must be read. 44.2.12 44.2.12.1 UHP UHP: Non-ISO IN Transfers Conditions: Consider the following sequence: 1. The Host controller issues an IN token. 2. The Device provides the IN data in a short packet. 3. The Host controller writes the received data to the system memory. 4. The Host controller is now supposed to carry out two Write transactions (TD status write and TD retirement write) to the system memory in order to complete the status update. 5. The Host controller raises the request for the first write transaction. By the time the transaction is completed, a frame boundary is crossed. 6. After completing the first write transaction, the Host controller skips the second write transaction. Consequence: When this error occurs, the Host controller tries the same IN token again. Problem Fix/Workaround This problem can be avoided if the system guarantees that the status update can be completed within the same frame. 44.2.12.2 UHP: ISO OUT transfers Conditions: Consider the following sequence: 1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the system memory. 2. When the Host controller is sending the ISO OUT data, because of system latencies, remaining bytes of the packet are not available. This results in a buffer underrun condition. 3. While there is an underrun condition, if the Host controller is in the process of bit-stuffing, it causes the Host controller to hang. Consequence: After the failure condition, the Host controller stops sending the SOF. This causes the connected device to go into suspend state. Problem Fix/Workaround This problem can be avoided if the system can guarantee that no buffer underrun occurs during the transfer. 808 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 44.2.12.3 UHP: Remote Wakeup Event Conditions: When a Remote Wakeup event occurs on a downstream port, the OHCI Host controller begins sending resume signaling to the device. The Host controller is supposed to send this resume signaling for 20 ms. However, if the driver sets the HcControl.HCFS into USBOPERATIONAL state during the resume event, then the Host controller terminates sending the resume signal with an EOP to the device. Consequence: If the Device does not recognize the resume (<20 ms) event then the Device remains in suspend state. Problem Fix/Workaround Host stack can do a port resume after it sets the HcControl.HCFS to USBOPERATIONAL. 44.2.13 44.2.13.1 USART USART: TXD Signal is floating in Modem and Hardware Handshaking mode. TXD signal should be pulled up in Modem and Hardware Handshaking mode. Problem Fix/Workaround TXD is multiplexed with PIO which integrates a pull up resistor. This internal pull-up must be enabled. 44.2.13.2 USART: DCD is Active High instead of Low The DCD signal is active at High level in the USART Modem Mode . DCD should be active at Low level. Problem Fix/Workaround Add an inverter. 809 6384D-ATARM-04-May-09 44.3 AT91SAM9G20 Errata - Revision "B" Parts Refer to Section 44.1 "Marking" on page 801. 44.3.1 44.3.1.1 Analog-to-digital Converter (ADC) ADC: Sleep Mode If Sleep mode is activated while there is no activity (no conversion is being performed), it will take effect only after a conversion occurs. Problem Fix/Workaround To activate sleep mode as soon as possible, it is recommended to write successively, ADC Mode Register (SLEEP) then ADC Control Register (START bit field); to start an analog-to-digital conversion, in order put ADC into sleep mode at the end of this conversion. 44.3.2 44.3.2.1 Boot ROM Boot ROM: ROM Code, Internal RC Usage with SAM-BA Boot through USB Booting from the internal RC oscillator (OSCSEL = 0) prevents using SAM-BA Boot through the USB device interface. Problem Fix/Workaround Use SAM-BA Boot through DBGU (or AT91SAM-ICE JTAG-ICE interface with SAM-BA GUI) if the internal RC oscillator must be used. Boot from the 32 kHz external oscillator (OSCEL =1) to use SAM-BA Boot through the USB. 44.3.2.2 Boot ROM: MCCK Remains Active The ROM boot sequence is as follows; - DataFlash on SPI0 NPCS0 - DataFlash on SPI0 NPCS1 - NAND FLash - SDCard - TWI - SAM-BA Boot MCCK is not disabled after SDCard boot program. This does not affect the TWI boot program but must be considered by any applications using SAM-BA boot. Problem Fix/Workaround None. 44.3.3 44.3.3.1 Error Corrected Code Controller (ECC) ECC: 1-bit ECC per 512 Words 1-bit ECC per 512 words is not functional. Problem Fix/Workaround Perform the ECC computation by software. 810 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 44.3.4 44.3.4.1 MCI MCI: Busy Signal of R1b responses is not taken in account The busy status of the card during the response (R1b) is ignored for the commands CMD7, CMD28, CMD29, CMD38, CMD42, CMD56. Additionally, for commands CMD42 and CMD56 a conflict can occur on data line0 if the MCI sends data to the card while the card is still busy.The behavior is correct for CMD12 command (STOP_TRANSFER). Problem Fix/Workaround None. 44.3.4.2 MCI: SDIO Interrupt does not work with slots other than A If there is 1-bit data bus width on slots other than slot A, the SDIO interrupt can not be captured. Th sample is made on the wrong data line. Problem Fix/Workaround None 44.3.4.3 MCI: Data Timeout Error Flag As the data Timeout error flag checking the Naac timing cannot rise, the MCI can be stalled waiting indefinitely the Data start bit. Problem Fix/Workaround A STOP command must be sent with a software timeout. 44.3.4.4 MCI: Data Write Operation and number of bytes The Data Write operation with a number of bytes less than 12 is impossible. Problem Fix/Workaround The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The BLKLEN or BCNT field are used to specify the real count number. 44.3.4.5 MCI: Flag Reset is not correct in half duplex mode In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be incorrect. These flags are reset correctly after a PDC channel enable. Problem Fix/Workaround Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the PDC channel by writing PDC_TXTEN or PDC_RXTEN. 811 6384D-ATARM-04-May-09 44.3.5 44.3.5.1 Reset Controller (RSTC) RSTC: Reset During SDRAM Accesses When a User Reset occurs during SDRAM read access, the SDRAM clock is turned off while data are ready to be read on the data bus. The SDRAM maintains the data until the clock restarts. If the user Reset is programmed to assert a general reset, the data maintained by the SDRAM leads to a data bus conflict and adversely affects the boot memories connected on the EBI: * NAND Flash boot functionality, if the system boots out of internal ROM. * NOR Flash boot, if the system boots on an external memory connected on the EBI CS0. Problem Fix/Workaround 1. Avoid User Reset to generate a system reset. 2. Trap the User Reset with an interrupt. In the interrupt routine, Power Down SDRAM properly and perform Peripheral and Processor Reset with software in assembler. Example with libV3. * The main code: //user reset interrupt setting // Configure AIC controller to handle SSC interrupts AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, sysc_handler ); // Enable SYSC interrupt in AIC AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS); *AT91C_RSTC_RMR = (0xA5<<24) | (0x4<<8) | AT91C_RSTC_URSTIEN; // AIC base address // System peripheral ID // Max priority AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED, // Level sensitive * The C SYS handler: extern void soft_user_reset(void); void sysc_handler(void){ //check if interrupt comes from RSTC if( (*AT91C_RSTC_RSR & AT91C_RSTC_URSTS ) == AT91C_RSTC_URSTS){ soft_user_reset(); //never reached while(1); } } * The assembler routine: 812 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary AREA TEST, CODE INCLUDEAT91SAM9xxx.inc EXPORTsoft_user_reset soft_user_reset ;disable IRQs MRS r0, CPSR ORR r0, r0, #0x80 MSR CPSR_c, r0 ;change refresh rate to block all data accesses LDR r0, =AT91C_SDRAMC_TR LDR r1, =1 STR r1, [r0] ;prepare power down command LDR r0, =AT91C_SDRAMC_LPR LDR r1, =2 ;prepare proc_reset and periph_reset LDR r2, =AT91C_RSTC_RCR LDR r3, =0xA5000005 ;perform power down command STR r1, [r0] ;perform proc_reset and periph_reset (in the ARM pipeline) STR r3, [r2] END 813 6384D-ATARM-04-May-09 44.3.6 44.3.6.1 Serial Peripheral Interface (SPI) SPI: Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0 If the SPI is used in the following configuration: * master mode * CPOL =1 and NCPHA = 0 * multiple chip selects used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock frequency equals the system clock frequency) and the other transfers set with SCBR not equal to 1 * transmit with the slowest chip select and then with the fastest one then an additional pulse will be generated on output PSCK during the second transfer. Problem Fix/Workaround Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and the others differ from 1 if CPHA = 0 and CPOL = 1. If all chip selects are configured with Baudrate = 1, the issue does not appear. 44.3.6.2 SPI: Baudrate set to 1 When Baudrate is set to 1 (i.e., when serial clock frequency equals the system clock frequency), and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15), an additional pulse is generated on output SPCK. No error occurs if BITS field equals 8,10,12,14 or 16 and Baudrate = 1. Problem Fix/Workaround None. 44.3.7 44.3.7.1 Serial Synchronous Controller (SSC) SSC: Unexpected RK clock cycle when RK outputs a clock during data transfer When the SSC receiver is used in the following configuration: * the internal clock divider is used (CKS =0 and DIV different from 0), * RK pin set as output and provides the clock during data transfer (CKO=2) * data sampled on RK falling edge (CKI =0) then, at the end of the data, the RK pin is set in high impedance which may be interpreted as an unexpected clock cycle. Problem Fix/Workaround Enable the pull-up on RK pin. 44.3.7.2 SSC: Incorrect first RK clock cycle when RK outputs a clock during data transfer When the SSC receiver is used in the following configuration: * RX clock is divided clock (CKS = 0 and DIV different from 0) * RK pin set as output and provides the clock during data transfer (CKO = 2) * data sampled on RK falling edge (CKI = 0) then the first clock cycle time generated by the RK pin is equal to MCK/(2 x (DIV +1)) instead of MCK/(2 x DIV). Problem Fix/Workaround 814 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary None. 44.3.7.3 SSC: Transmitter Limitations in Slave Mode If TK is programmed as output and TF is programmed as input, it is impossible to emit data when start of edge (rising or falling) of synchro with a Start Delay equal to zero. Problem Fix/Workaround None. 44.3.7.4 SSC: Periodic Transmission Limitations in Master Mode If Last Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent. Problem Fix/Workaround None. 44.3.8 44.3.8.1 Shutdown Controller (SHDWC) SHDWC: SHDN Signal may be Driven to Low Level Voltage During Device Power-on If only VDDBU is powered during boot sequence (No VDDCORE), the SHDN signal may be driven to low level voltage after a delay.This delay is linked to the startup time of the slow clock selected by OSCSEL signal. If SHDN pin is connected to the Enable pin (EN) of the VDDCORE regulator, VDDCORE establishment does not occur and the system does not start. Problem Fix/Workaround 1. VDDCORE must be established within the delay corresponding to the startup time of the slow clock selected by OSCSEL. 2. Add a glue logic to latch the rising edge of the SHDN signal. The reset of the latch output (EN_REG) can be connected to a PIO and used to enter the shutdown mode. 44.3.9 44.3.9.1 Static Memory Controller (SMC) SMC: Chip Select Parameters Modification The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if accesses are performed on this CS during the modification. For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code from a memory connected on this CS0, may lead to unpredictable behavior. Problem Fix/Workaround The code used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory connected to another Chip Select 44.3.10 44.3.10.1 System Controller (SYSC) SYSC: Possible Event Loss when reading RTT_SR If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when the RTT_SR is read, the corresponding bit might be cleared. This can lead to the loss of this event. Problem Fix/Workaround The software must handle an RTT event as an interrupt and should not poll RTT_SR. 815 6384D-ATARM-04-May-09 44.3.11 44.3.11.1 Two-wire Interface (TWI) TWI: RXRDY Flag is not reset by a SOFTWARE Reset The RXRDY Flag is not reset when a Software reset is performed. Problem Fix/Workaround After a Software Reset, the Register TWI_RHR must be read. 44.3.12 44.3.12.1 UHP UHP: Non-ISO IN Transfers Conditions: Consider the following sequence: 1. The Host controller issues an IN token. 2. The Device provides the IN data in a short packet. 3. The Host controller writes the received data to the system memory. 4. The Host controller is now supposed to carry out two Write transactions (TD status write and TD retirement write) to the system memory in order to complete the status update. 5. The Host controller raises the request for the first write transaction. By the time the transaction is completed, a frame boundary is crossed. 6. After completing the first write transaction, the Host controller skips the second write transaction. Consequence: When this error occurs, the Host controller tries the same IN token again. Problem Fix/Workaround This problem can be avoided if the system guarantees that the status update can be completed within the same frame. 44.3.12.2 UHP: ISO OUT transfers Conditions: Consider the following sequence: 1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the system memory. 2. When the Host controller is sending the ISO OUT data, because of system latencies, remaining bytes of the packet are not available. This results in a buffer underrun condition. 3. While there is an underrun condition, if the Host controller is in the process of bit-stuffing, it causes the Host controller to hang. Consequence: After the failure condition, the Host controller stops sending the SOF. This causes the connected device to go into suspend state. Problem Fix/Workaround This problem can be avoided if the system can guarantee that no buffer underrun occurs during the transfer. 816 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 44.3.12.3 UHP: Remote Wakeup Event Conditions: When a Remote Wakeup event occurs on a downstream port, the OHCI Host controller begins sending resume signaling to the device. The Host controller is supposed to send this resume signaling for 20 ms. However, if the driver sets the HcControl.HCFS into USBOPERATIONAL state during the resume event, then the Host controller terminates sending the resume signal with an EOP to the device. Consequence: If the Device does not recognize the resume (<20 ms) event then the Device remains in suspend state. Problem Fix/Workaround Host stack can do a port resume after it sets the HcControl.HCFS to USBOPERATIONAL. 44.3.13 44.3.13.1 USART USART: TXD Signal is floating in Modem and Hardware Handshaking Mode. TXD signal should be pulled up in Modem and Hardware Handshaking mode. Problem Fix/Workaround TXD is multiplexed with PIO which integrates a pull up resistor. This internal pull-up must be enabled. 44.3.13.2 USART: DCD is Active High instead of Low The DCD signal is active at High level in the USART Modem Mode . DCD should be active at Low level. Problem Fix/Workaround Add an inverter. 817 6384D-ATARM-04-May-09 818 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Revision History Change Request Ref. 6262 Doc. Rev 6384D Comments Section 41.6 "ADC", former Channel Conversion TIme and ADC Clock table and former Transfer Characteritics table replaced by Table 41-18, "ADC Characteristics 9-bit Mode" and Table 41-19, "ADC Characteristics 10-bit Mode". Section 44.2 "AT91SAM9G20 Errata - Revision "A" Parts", added Section 44.2.2.1 "Boot ROM: ROM Code, Internal RC Usage with SAM-BA Boot through USB". 6238 Doc. Rev 6384C Comments Overview: "Features", Section 4.3 "247-ball TFBGA Package Outline", Section 4.4 "247-ball TFBGA Package Pinout" added 247-ball TFBGA package information. Section 10.4.6 "Multimedia Card Interface", compatibility with MultiMedia Card spec v3.11, SD Memory Card spec v1.1. Table 3-1, Signal Description and Table 10-4, "Multiplexing on PIO Controller C" EF100 removed. ADC: Table 40-2, "Register Mapping" offset for Channel Data Register 3 is 0x3c. TWI: Section 31.7.4 "Master Transmitter Mode", updated with auto-stop functionality. Electrical Characteristics: Section "Shown below is an example of the implementation on the AT91SAM9G20-EK Rev.C.", added exception information for MLR B. Table 41-6, "XIN Clock Electrical Characteristics"added VIN, Section 41.1 "Absolute Maximum Ratings", added junction temperature Mechanical Characteristics: Section 42.2 "247-ball TFBGA Package Drawing", added to datasheet. Change Request Ref. 6079 6080 6148 6044 6050 6079 6163 rfo 6079 819 6384D-ATARM-04-May-09 Doc. Rev 6384C Comments (Continued) Ordering Information: Table 43-1, "AT91SAM9G20 Ordering Information"added MRL B ordering information. Errata: Section 44.2 "AT91SAM9G20 Errata - Revision "A" Parts" Section 44.2.2 "Boot ROM", Section 44.2.2.2 "Boot ROM: MCCK Remains Active", added to errata. Section 44.2.3 "Error Corrected Code Controller (ECC)" Section 44.2.3.1 "ECC: 1-bit ECC per 512 Words" added to errata. Section 44.2.4.2 "MCI: SDIO Interrupt does not work with slots other than A", syntax updated. Section 44.2.8 "Shutdown Controller (SHDWC)", Section 44.2.8.1 "SHDWC: SHDN Signal may be Driven to Low Level Voltage During Device Power-on", added to errata. Section 44.3 "AT91SAM9G20 Errata - Revision "B" Parts"; added to errata. Section 44.3.1 "Analog-to-digital Converter (ADC)", Section 44.3.2.1 "Boot ROM: ROM Code, Internal RC Usage with SAM-BA Boot through USB", added to errata. Section 44.3.2.2 "Boot ROM: MCCK Remains Active", added to errata. Section 44.3.3 "Error Corrected Code Controller (ECC)" Section 44.3.3.1 "ECC: 1-bit ECC per 512 Words" added to errata. Section 44.3.4.2 "MCI: SDIO Interrupt does not work with slots other than A", syntax updated. Section 44.3.8 "Shutdown Controller (SHDWC)", Section 44.3.8.1 "SHDWC: SHDN Signal may be Driven to Low Level Voltage During Device Power-on", added to errata. Change Request Ref. 6079 6045 6168 6169 6069 6045 6070 6168 6169 6069 820 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Doc. Rev 6384B Comments Change Request Ref. 5846 5931 5935 6022 Overview "Features" on page 1, Debug Unit (DBGU) updated. Section 10.4.3 "USART", "Optional Manchester Encoding" added to list of USART features. Section 8.1.1.1 "BMS = 1, Boot on Embedded ROM", - SDCard, (boot ROM does not support high capacity SDCards) clarification added. Signal Description, Table 3-1, added GNDPLL to table. Section 6.6 "Shutdown Logic Pins", updated with external pull-up requirement. rfo AT91SAM9G20 Boot Program Section 13.3 "Device Initialization", updated "Enable the user reset" removed from initialization steps. Section 13.8 "SDCard Boot" added (high capactiy SDCards not support by boot ROM) Section 13.11 "Hardware and Software Constraints" added footnote (1) "Boot ROM does not support high capacity SDCards." DBGU Section 28.1 "Overview", added text: "The Debug Unit two-pin UART can be used stand-alone for general purpose serial communication." PMC Section 26.9.11 "PMC Master Clock Register": bitfiedld description for "PDIV: Processor Clock Division", Processor Clock replaced Master Clock in description. Electrical Characteristics: Section 41.8 "Core Power Supply POR Characteristics", updated with caution on power-up, Figure 41-2. "VDDCORE and VDDIO Constraints at Startup" updated, and Board Schematics added to section. 41.11.2 "SPI" Timings: The titles of the figures listed below have been updated. Figure 41-7. "SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL =1 and NCPHA = 0)" Figure 41-8. "SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL and NCPHA = 1)" Figure 41-9. "SPI Slave Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)" Figure 41-10. "SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)" Table 41-4, "Power Consumption by Peripheral in Active Mode" updatedvalues in Consumption column. Table 41-15, "PLLA Characteristics" IPLL active mode, current consumption is 8 mA. Table 41-3, "Power Consumption for Different Modes" Active mode, "all peripheral clocks de-activated". Errata: Section 44.2.9 "Static Memory Controller (SMC)", added to datasheet with the errata listed below: Section 44.2.9.1 "SMC: Chip Select Parameters Modification" 5590 5934 5935 5846/ 5847 6384 5943 5592 5771 5802 5642 821 6384D-ATARM-04-May-09 Doc. Rev 6384A Comments First issue Change Request Ref. 822 AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary Table of Contents 1 2 3 4 Description ............................................................................................... 3 AT91SAM9G20 Block Diagram ............................................................... 4 Signal Description .................................................................................. 5 Package and Pinout ................................................................................. 9 4.1 4.2 4.3 4.4 217-ball LFBGA Package Outline ........................................................................9 217-ball LFBGA Pinout ......................................................................................10 247-ball TFBGA Package Outline ......................................................................11 247-ball TFBGA Package Pinout .......................................................................12 5 Power Considerations ........................................................................... 13 5.1 5.2 5.3 Power Supplies ..................................................................................................13 Power Consumption ...........................................................................................13 Programmable I/O Lines ....................................................................................13 6 I/O Line Considerations ......................................................................... 14 6.1 6.2 6.3 6.4 6.5 6.6 6.7 JTAG Port Pins ..................................................................................................14 Test Pin ..............................................................................................................14 Reset Pins ..........................................................................................................14 PIO Controllers ...................................................................................................14 I/O Line Drive Levels ..........................................................................................14 Shutdown Logic Pins ..........................................................................................14 Slow Clock Selection ..........................................................................................15 7 Processor and Architecture .................................................................. 15 7.1 7.2 7.3 7.4 ARM926EJ-S Processor ....................................................................................15 Bus Matrix ..........................................................................................................16 Peripheral DMA Controller .................................................................................17 Debug and Test Features ..................................................................................18 8 Memories ................................................................................................ 19 8.1 8.2 Embedded Memories .........................................................................................20 External Memories .............................................................................................21 9 System Controller .................................................................................. 23 9.1 9.2 9.3 System Controller Block Diagram ......................................................................24 Reset Controller .................................................................................................25 Shutdown Controller ...........................................................................................25 i 6384D-ATARM-04-May-09 9.4 9.5 9.6 9.7 9.8 9.9 Clock Generator .................................................................................................25 Power Management Controller ..........................................................................26 Periodic Interval Timer .......................................................................................27 Watchdog Timer .................................................................................................27 Real-time Timer ..................................................................................................27 General-purpose Back-up Registers ..................................................................27 9.10 Advanced Interrupt Controller ............................................................................27 9.11 Debug Unit .........................................................................................................28 9.12 Chip Identification ...............................................................................................28 10 Peripherals ............................................................................................. 29 10.1 User Interface .....................................................................................................29 10.2 Identifiers ............................................................................................................29 10.3 Peripheral Signal Multiplexing on I/O Lines .......................................................30 10.4 Embedded Peripherals .......................................................................................34 11 ARM926EJ-S Processor Overview ....................................................... 39 11.1 Overview ............................................................................................................39 11.2 Block Diagram ....................................................................................................40 11.3 ARM9EJ-S Processor ........................................................................................41 11.4 CP15 Coprocessor .............................................................................................49 11.5 Memory Management Unit (MMU) .....................................................................51 11.6 Caches and Write Buffer ....................................................................................53 11.7 Bus Interface Unit ...............................................................................................55 12 AT91SAM9G20 Debug and Test ........................................................... 57 12.1 Overview ............................................................................................................57 12.2 Block Diagram ....................................................................................................58 12.3 Application Examples .........................................................................................59 12.4 Debug and Test Pin Description ........................................................................60 12.5 Functional Description ........................................................................................61 13 AT91SAM9G20 Boot Program .............................................................. 73 13.1 Overview ............................................................................................................73 13.2 Flow Diagram .....................................................................................................73 13.3 Device Initialization ............................................................................................75 13.4 Valid Image Detection ........................................................................................77 13.5 Serial Flash Boot ................................................................................................78 13.6 DataFlash Boot Sequence .................................................................................79 ii AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 13.7 NAND Flash Boot ...............................................................................................81 13.8 SDCard Boot ......................................................................................................81 13.9 EEPROM Boot ...................................................................................................81 13.10 SAM-BA Boot .....................................................................................................82 13.11 Hardware and Software Constraints ..................................................................86 14 Reset Controller (RSTC) ........................................................................ 87 14.1 Overview ............................................................................................................87 14.2 Block Diagram ....................................................................................................87 14.3 Functional Description ........................................................................................88 14.4 Reset Controller (RSTC) User Interface ............................................................96 15 Real-time Timer (RTT) .......................................................................... 101 15.1 Overview ..........................................................................................................101 15.2 Block Diagram ..................................................................................................101 15.3 Functional Description ......................................................................................101 15.4 Real-time Timer (RTT) User Interface ..............................................................103 16 Periodic Interval Timer (PIT) ............................................................... 107 16.1 Overview ..........................................................................................................107 16.2 Block Diagram ..................................................................................................107 16.3 Functional Description ......................................................................................107 16.4 Periodic Interval Timer (PIT) User Interface .....................................................109 17 Watchdog Timer (WDT) ....................................................................... 113 17.1 Overview ..........................................................................................................113 17.2 Block Diagram ..................................................................................................113 17.3 Functional Description ......................................................................................114 17.4 Watchdog Timer (WDT) User Interface ............................................................116 18 Shutdown Controller (SHDWC) .......................................................... 119 18.1 Overview ..........................................................................................................119 18.2 Block Diagram ..................................................................................................119 18.3 I/O Lines Description ........................................................................................119 18.4 Product Dependencies .....................................................................................119 18.5 Functional Description ......................................................................................120 18.6 Shutdown Controller (SHDWC) User Interface ................................................121 19 AT91SAM9G20 Bus Matrix .................................................................. 125 19.1 Overview ..........................................................................................................125 iii 6384D-ATARM-04-May-09 19.2 Memory Mapping .............................................................................................125 19.3 Special Bus Granting Techniques ....................................................................125 19.4 Arbitration .........................................................................................................126 19.5 Bus Matrix (MATRIX) User Interface ................................................................128 19.6 Chip Configuration User Interface ....................................................................133 20 AT91SAM9G20 External Bus Interface .............................................. 135 20.1 Overview ..........................................................................................................135 20.2 Block Diagram ..................................................................................................136 20.3 I/O Lines Description ........................................................................................137 20.4 Application Example .........................................................................................139 20.5 Product Dependencies .....................................................................................142 20.6 Functional Description ......................................................................................142 20.7 Implementation Examples ................................................................................150 21 Static Memory Controller (SMC) ......................................................... 159 21.1 Overview ..........................................................................................................159 21.2 I/O Lines Description ........................................................................................159 21.3 Multiplexed Signals ..........................................................................................159 21.4 Application Example .........................................................................................160 21.5 Product Dependencies .....................................................................................160 21.6 External Memory Mapping ...............................................................................161 21.7 Connection to External Devices .......................................................................161 21.8 Standard Read and Write Protocols .................................................................165 21.9 Automatic Wait States ......................................................................................174 21.10 Data Float Wait States .....................................................................................179 21.11 External Wait ....................................................................................................183 21.12 Slow Clock Mode .............................................................................................189 21.13 Asynchronous Page Mode ...............................................................................192 21.14 Static Memory Controller (SMC) User Interface ...............................................195 22 SDRAM Controller (SDRAMC) ............................................................ 201 22.1 Overview ..........................................................................................................201 22.2 I/O Lines Description ........................................................................................201 22.3 Application Example .........................................................................................202 22.4 Product Dependencies .....................................................................................204 22.5 Functional Description ......................................................................................206 22.6 SDRAM Controller (SDRAMC) User Interface .................................................213 iv AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 23 Error Corrected Code Controller (ECC) ............................................. 223 23.1 Overview ..........................................................................................................223 23.2 Block Diagram ..................................................................................................223 23.3 Functional Description ......................................................................................224 23.4 Error Corrected Code Controller (ECC) User Interface ....................................229 23.5 Registers for 1 ECC for a page of 512/1024/2048/4096 bytes ........................240 23.6 Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word .......................................................................................................242 23.7 Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word .......................................................................................................250 24 Peripheral DMA Controller (PDC) ....................................................... 267 24.1 Overview ..........................................................................................................267 24.2 Block Diagram ..................................................................................................268 24.3 Functional Description ......................................................................................268 24.4 Peripheral DMA Controller (PDC) User Interface .............................................271 25 Clock Generator ................................................................................... 281 25.1 Overview ..........................................................................................................281 25.2 Slow Clock Crystal Oscillator ...........................................................................281 25.3 Slow Clock RC Oscillator .................................................................................281 25.4 Main Oscillator .................................................................................................281 25.5 Divider and PLL Block ......................................................................................283 26 Power Management Controller (PMC) ................................................ 285 26.1 Overview ..........................................................................................................285 26.2 Master Clock Controller ....................................................................................285 26.3 Processor Clock Controller ..............................................................................286 26.4 USB Clock Controller .......................................................................................286 26.5 Peripheral Clock Controller ..............................................................................287 26.6 Programmable Clock Output Controller ...........................................................287 26.7 Programming Sequence ..................................................................................287 26.8 Clock Switching Details ....................................................................................293 26.9 Power Management Controller (PMC) User Interface ....................................297 27 Advanced Interrupt Controller (AIC) .................................................. 315 27.1 Overview ..........................................................................................................315 27.2 Block Diagram ..................................................................................................316 27.3 Application Block Diagram ...............................................................................316 v 6384D-ATARM-04-May-09 27.4 AIC Detailed Block Diagram .............................................................................316 27.5 I/O Line Description ..........................................................................................317 27.6 Product Dependencies .....................................................................................317 27.7 Functional Description ......................................................................................318 27.8 Advanced Interrupt Controller (AIC) User Interface .........................................328 28 Debug Unit (DBGU) .............................................................................. 341 28.1 Overview ..........................................................................................................341 28.2 Block Diagram ..................................................................................................342 28.3 Product Dependencies .....................................................................................343 28.4 UART Operations .............................................................................................343 28.5 Debug Unit (DBGU) User Interface .................................................................350 29 Parallel Input Output Controller (PIO) ................................................ 365 29.1 Overview ..........................................................................................................365 29.2 Block Diagram ..................................................................................................366 29.3 Product Dependencies .....................................................................................367 29.4 Functional Description ......................................................................................368 29.5 I/O Lines Programming Example .....................................................................372 29.6 Parallel Input/Output Controller (PIO) User Interface .......................................374 30 Serial Peripheral Interface (SPI) ......................................................... 391 30.1 Overview ..........................................................................................................391 30.2 Block Diagram ..................................................................................................392 30.3 Application Block Diagram ...............................................................................392 30.4 Signal Description ...........................................................................................393 30.5 Product Dependencies .....................................................................................393 30.6 Functional Description ......................................................................................394 30.7 Serial Peripheral Interface (SPI) User Interface ...............................................403 31 Two-wire Interface (TWI) ..................................................................... 417 31.1 Overview ..........................................................................................................417 31.2 List of Abbreviations .........................................................................................417 31.3 Block Diagram ..................................................................................................418 31.4 Application Block Diagram ...............................................................................418 31.5 Product Dependencies .....................................................................................419 31.6 Functional Description ......................................................................................419 31.7 Master Mode ....................................................................................................421 31.8 Multi-master Mode ...........................................................................................433 vi AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 31.9 Slave Mode ......................................................................................................436 31.10 Two-wire Interface (TWI) User Interface ..........................................................444 32 Universal Synchronous Asynchronous Receiver Transmitter (USART) ................................................................................................ 459 32.1 Overview ..........................................................................................................459 32.2 Block Diagram ..................................................................................................460 32.3 Application Block Diagram ...............................................................................461 32.4 I/O Lines Description .......................................................................................462 32.5 Product Dependencies .....................................................................................463 32.6 Functional Description ......................................................................................464 32.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface ...............................................................................495 33 Synchronous Serial Controller (SSC) ................................................ 517 33.1 Overview ..........................................................................................................517 33.2 Block Diagram ..................................................................................................518 33.3 Application Block Diagram ...............................................................................518 33.4 Pin Name List ...................................................................................................519 33.5 Product Dependencies .....................................................................................519 33.6 Functional Description ......................................................................................519 33.7 SSC Application Examples ..............................................................................531 33.8 Syncrhronous Serial Controller (SSC) User Interface ......................................533 34 Timer Counter (TC) .............................................................................. 555 34.1 Overview ..........................................................................................................555 34.2 Block Diagram ..................................................................................................556 34.3 Pin Name List ...................................................................................................557 34.4 Product Dependencies .....................................................................................557 34.5 Functional Description ......................................................................................558 34.6 Timer Counter (TC) User Interface ..................................................................571 35 MultiMedia Card Interface (MCI) ......................................................... 589 35.1 Overview ..........................................................................................................589 35.2 Block Diagram ..................................................................................................590 35.3 Application Block Diagram ...............................................................................591 35.4 Pin Name List ..................................................................................................591 35.5 Product Dependencies .....................................................................................591 35.6 Bus Topology ...................................................................................................592 vii 6384D-ATARM-04-May-09 35.7 MultiMedia Card Operations ............................................................................595 35.8 SD/SDIO Card Operations ...............................................................................603 35.9 MultiMedia Card Interface (MCI) User Interface ..............................................604 36 Ethernet MAC 10/100 (EMAC) ............................................................. 623 36.1 Overview ..........................................................................................................623 36.2 Block Diagram ..................................................................................................623 36.3 Functional Description ......................................................................................624 36.4 Programming Interface .....................................................................................635 36.5 Ethernet MAC 10/100 (EMAC) User Interface .................................................638 37 USB Device Port (UDP) ........................................................................ 671 37.1 Overview ..........................................................................................................671 37.2 Block Diagram ..................................................................................................672 37.3 Product Dependencies .....................................................................................672 37.4 Typical Connection ...........................................................................................674 37.5 Functional Description ......................................................................................675 37.6 USB Device (UDP) User Interface ...................................................................690 38 USB Host Port (UHP) ........................................................................... 709 38.1 Overview ..........................................................................................................709 38.2 Block Diagram ..................................................................................................709 38.3 Product Dependencies .....................................................................................710 38.4 Functional Description ......................................................................................710 38.5 Typical Connection ...........................................................................................712 39 Image Sensor Interface (ISI) ................................................................ 713 39.1 Overview ..........................................................................................................713 39.2 Block Diagram ..................................................................................................714 39.3 Functional Description ......................................................................................714 39.4 Image Sensor Interface (ISI) User Interface ....................................................723 40 Analog-to-digital Converter (ADC) ..................................................... 743 40.1 Overview ..........................................................................................................743 40.2 Block Diagram ..................................................................................................743 40.3 Signal Description ............................................................................................744 40.4 Product Dependencies .....................................................................................744 40.5 Functional Description ......................................................................................745 40.6 Analog-to-Digital Converter (ADC) User Interface ...........................................750 viii AT91SAM9G20 Preliminary 6384D-ATARM-04-May-09 AT91SAM9G20 Preliminary 41 AT91SAM9G20 Electrical Characteristics ......................................... 763 41.1 Absolute Maximum Ratings .............................................................................763 41.2 DC Characteristics ...........................................................................................764 41.3 Power Consumption .........................................................................................765 41.4 Clock Characteristics .......................................................................................767 41.5 Crystal Oscillator Characteristics .....................................................................769 41.6 ADC ..................................................................................................................773 41.7 USB Transceiver Characteristics .....................................................................775 41.8 Core Power Supply POR Characteristics .........................................................776 41.9 EBI Timings ......................................................................................................779 41.10 SDRAMC Timings ............................................................................................782 41.11 Peripheral Timings ...........................................................................................784 42 AT91SAM9G20 Mechanical Characteristics ...................................... 796 42.1 217-ball LFBGA Package Drawing ..................................................................796 42.2 247-ball TFBGA Package Drawing ..................................................................798 43 AT91SAM9G20 Ordering Information ................................................ 800 44 AT91SAM9G20 Errata .......................................................................... 801 44.1 Marking ............................................................................................................801 44.2 AT91SAM9G20 Errata - Revision "A" Parts .....................................................802 44.3 AT91SAM9G20 Errata - Revision "B" Parts .....................................................810 ix 6384D-ATARM-04-May-09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM Technical Support AT91SAM Support Sales Contacts www.atmel.com/contacts/ Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2009 Atmel Corporation. All rights reserved. Atmel (R), logo and combinations thereof DataFlash(R), SAM-BA (R) and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM (R), Thumb (R) and the ARMPowered logo (R) and others are registered trademarks or trademarks ARM Ltd. Windows (R) and others are registered trademarks or trademarks of Microsoft Corporation in the US and/or other countries. Other terms and product names may be trademarks of others. 6384D-ATARM-04-May-09 |
Price & Availability of AT91SAM9G201
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |